Abstract: To enable a method and a base chip (200) for monitoring, by means of at least one base chip (200), the operation of at least one microcontroller unit (300) that is intended for at least one application and is associated with a system (100) to be further developed in such a way a reset of the microcontroller unit (300) only takes place under defined conditions, it is proposed that a reset (R) of the microcontroller unit (300) is caused if at least one special sequence, and particularly at least one drive or access sequence assigned to the reset operation (R), is applied to the base chip (200).

Abstract: A transceiver for a serial data bus is provided which transceiver includes error management. In a first example embodiment of a transceiver, error management is provided which supplies an error signal when the data bus lines are active and the receiving line simultaneously is inactive. In a second example embodiment of a transceiver, error management is provided which triggers an error signal when the transmission line is active for a longer period than a predetermined time interval, which error signal is cancelled when both the transmission line is inactive and the receiving line is active.

Abstract: In order further to develop a method for changing over a serially networked system (100), in particular a serial databus system, from subnetwork operation (T), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and is not addressed and/or not activated by the signal level (40, 42, 44) of the data traffic on the system (100), to full network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) are addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), together with a corresponding system (100) in such a way that the nodes (22, 28) and/or the users (32, 38) in the network, i.e.

Abstract: An integrated circuit having a system base chip (1) that has basic functions for a transmitting and/or receiving system for a vehicle data bus, namely at least a system voltage supply (3), a system reset (3) and a monitoring function (2), an interface circuit (4, 5) that, in a self-contained fashion, runs at least parts of a data bus protocol, and in particular the LIN (Local Interconnect Network) protocol, that performs detection of the bit-rate of received data, and that is capable of passing on at least one received or transmitted byte. a serial/parallel converter (5) that makes use in its conversion of the bit-rate detected by the interface circuit (4, 5).

Abstract: A reset arrangement for a microcontroller and/or further hardware circuits to be reset should be optimally adaptable to the requirements of the microcontroller and/or the hardware circuits. To this end, the reset arrangement is formed in such a way that it is capable of applying a reset signal to the microcontroller via a reset line, supplies a first reset signal upon a system cold start of the reset arrangement and the microcontroller, the duration of this first reset signal being chosen to be such that any provided type of microcontroller starts reliably, is programmed with a second reset signal after a system cold start of the microcontroller, the duration of this second reset signal being adapted to the requirements of the microcontroller, and supplies the second, programmed reset signal as a reset signal at subsequent cold or hot starts.

Abstract: To improve a method as well as a circuit arrangement (100) for detecting the ground offset of parts of a network system, more particularly for checking the ground contact between network control units where data are sent and received over at least one bus system so that, on the one hand, prior to a breakdown event already a warning can be obtained in this respect that the state of the ground connection between the control units is no longer optimal but, on the other hand, ground defects are not shown by mistake, there is proposed 'a! that in the idle state at least one bus line provided for receiving data and/or of at least one receiver line (24), after a predefinable first time period has elapsed, the level voltage (14) of this at least one bus line is scanned and compared with at least one predefinable limit or reference potential value, 'b! in that if the limit or reference potential value is exceeded, at least one ground error signal is generated, and 'c! in that in dependence on the fact whether until a

Abstract: To further develop a method and a base chip (200) for monitoring the operation of at least one microcontroller that is intended for at least one application and is associated with a system (100) in such a way that a failure in the reset function can be reliably detected and the conclusions that need to be drawn for system-related reasons can be drawn, it is proposed that: the microcontroller unit (300) has at least one monitoring module (10) associated with it and that; the fact that a reset of the microcontroller unit (300) has taken place is acknowledged to the monitoring module (10) by means of at least one confirming signal.

Abstract: In order further to develop a method for changing over a serially networked system (100), in particular a serial databus system, from subnetwork operation (T), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and is not addressed and/or not activated by the signal level (40, 42, 44) of the data traffic on the system (100), to full network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) are addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), together with a corresponding system (100) in such a way that the nodes (22, 28) and/or the users (32, 38) in the network, i.e.

Abstract: A circuit arrangement for vehicles for generating at least two DC output voltages (VA1, VA2) from at least one DC input voltage (VE), wherein the DC output voltages (VA1, VA2) are smaller than the DC input voltage (VE), the circuit arrangement comprising voltage regulating means (3, 4; 13, 14) for generating the DC output voltages (VA1, VA2), and wherein the DC input voltage (VE) is applied to a DC/DC converter (2; 12) which can be switched on or off by a control means (5; 15) and supplies a lower voltage than the DC input voltage (VE) to the voltage regulating means.

Abstract: A circuit arrangement for the processing of binary signals. The circuit arrangement includes at least one logic arrangement for outputting a binary output signal and at least one storage arrangement for storing the binary output signal, wherein at least one of the storage arrangements includes a number of storage cells.

Abstract: In a circuit arrangement for error recognition of a two-wire data bus through which transmitted, dominant bits are differentially transmitted on the two bus lines, it is proposed that the arrangement comprises means (4) for measuring the differential current, by means of which the difference of the drive currents with which the two bus lines are driven is measured in a transmitter when transmitting dominant bits on the data bus, and in that evaluation means (5) are provided which supply an error signal when the difference between the drive currents exceeds a predetermined limit value.

Abstract: In a bus system with a low-power phase, in which bus members are in a state of reduced current consumption and leave this state when the bus lines (1, 2) are active for a longer period than a predetermined time interval, the function of the bus in the low-power phase is monitored in that a first participant (3) cyclically transmits at least one pulse on the bus during the low-power phase, which pulse has a duration that is shorter than the predetermined time interval and is received and evaluated at least by a second bus member (4) for the purpose of monitoring the bus lines (1, 2).

Abstract: A reset arrangement (1) for a microcontroller (3) and/or further hardware circuits to be reset should be optimally adaptable to the requirements of the microcontroller and/or the hardware circuits.

Abstract: In a first embodiment of a transceiver according to the invention for a serial data bus, means (1) for error management are provided which supply an error signal when the data bus lines (2, 3) are active and when the receiving line simultaneously signalizes an inactive bus, said error signal having the effect that the transceiver no longer acts actively on the data bus. In a second embodiment of the transceiver according to the invention, means (1) for error management are provided in the transceiver, which means comprise a timer circuit which triggers an error signal when the transmission line is active for a longer period than a predetermined time interval, which error signal is cancelled only when the transmission line signalizes an inactive bus and the receiving line signalizes an active bus.

Abstract: In a circuit arrangement for error recognition of a two-wire data bus through which transmitted, dominant bits are differentially transmitted on the two bus lines, it is proposed that the arrangement comprises means (4) for measuring the differential current, by means of which the difference of the drive currents with which the two bus lines are driven is measured in a transmitter when transmitting dominant bits on the data bus, and in that evaluation means (5) are provided which supply an error signal when the difference between the drive currents exceeds a predetermined limit value.