Abstract: A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: The present invention relates to a method for routing data paths in a semiconductor chip with a plurality of layers. The inventive method comprises the steps of wiring a launching clock path and a receiving clock path on one or more layers according to at least one predetermined condition, performing one or more timing tests for determining any critical paths, and determining a weight function for every layer of each critical path. Said weight function is defined as the difference between a property of the launching clock tree and the same property of the receiving clock tree on said layer. If said weight function is positive for any layer, the wiring of the data path is not allowed on said layer. Preferably the remaining layers are chosen in such a way that a local variation of the delay on said layer is minimal.