Abstract: Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

Abstract: Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

Abstract: Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

Abstract: An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself.

Abstract: An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.

Abstract: A method and a device for determining an output sequence of output elements from an input sequence of input elements is provided, the method or the device being implemented according to a decision feedback equalizer. The adaptation of coefficients of the equalizer is performed on the basis of an estimated error determined as a function of a scaling (a, c0). According to the invention the scaling (a, c0) is determined such that it differs from a nominal input value by a deviation value during transmission without symbol interference. The deviation value is dependent on non-compensatable inter-symbol interference.

Abstract: An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself.

Abstract: A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.

Abstract: An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.

Abstract: A method and a device for determining an output sequence of output elements from an input sequence of input elements is provided, the method or the device being implemented according to a decision feedback equalizer. The adaptation of coefficients of the equalizer is performed on the basis of an estimated error determined as a function of a scaling (a, c0). According to the invention the scaling (a, c0) is determined such that it differs from a nominal input value by a deviation value during transmission without symbol interference. The deviation value is dependent on non-compensatable inter-symbol interference.

Abstract: An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.

Abstract: A processor is disclosed, in which a block memory (ADM), a search domain memory (SDM), a two-dimensional processor/memory cell field (PRA) and a control unit (CTRL) are preferably monolithically integrated in a semiconductor chip. The word width of toe search domain memory (SDM) is organised so that the processor/register cell field (PRA) is supplied, in parallel per system cycle (CLK) with data (SF) on picture elements of a new complete column of the search domain. At the same time, a control sequence is stored in the control unit (CTRL). The control sequence supplies data flow control signals (DFC) and addresses (ADR1, ADR2) to the block memory and search domain memory in parallel, per system cycle. The control unit essentially consists of a shift register into which external control signals (CD) of any desired control sequences may be written.