Abstract: A device for modifying an AC voltage has an input for connecting to an AC voltage source and an output for connecting to a load circuit. An interrupter is designed such that, within a time window, the output can be disconnected from the AC voltage source. The time window has a time delay from the zero crossing of the voltage of the AC voltage source. At the output, the device has a terminator that is designed, together with the interrupter, such that the voltage at the output has a predefined or predefinable value in the time window. The device also includes a pulse shape generator for generating a predetermined or predeterminable pulse shape, and a control that actuates the terminator and the interrupter such that the voltage curve at the output can be modified according to the pulse shape predetermined by the pulse shape generator.

Abstract: A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instructions to the plurality of discrete instruction queues.

Abstract: The invention relates to a device (1) for modifying an AC voltage, wherein the device (1) comprises an input (1) for connecting to an AC voltage source and an output (3) for connecting to a load circuit. The device (1) comprises an interrupter (15) that is designed such that, within at least one time window (35), the output (3) can be disconnected from the AC voltage source, wherein the time window (35) has a time delay (36) from the zero crossing (40) of the voltage of the AC voltage source. At the output (3), the device comprises a terminator (20) that is designed, in particular together with the interrupter (15), such that the voltage at the output (3) of the device (1) has a predefined or predefinable value (37) in the time window (35).

Abstract: A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instructions to the plurality of discrete instruction queues.

Abstract: The invention relates to a processor comprising several control units and functional blocks which can be commonly accessed by the control units. The processor also includes a central control unit which determines the access of the control units to the functional blocks. At least two control units are embodied as control units of a different type.