Patents by Inventor Matthias U. Lehr

Matthias U. Lehr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal line layout based on line shifting
    Patent number: 9898572
    Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Melde, Matthias U. Lehr, Thomas Herrmann, Jens Hassmann, Moritz Andreas Meyer, Rakesh Kumar Kuncha
  • METAL LINE LAYOUT BASED ON LINE SHIFTING
    Publication number: 20170235867
    Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Inventors: Thomas Melde, Matthias U. Lehr, Thomas Herrmann, Jens Hassmann, Moritz Andreas Meyer, Rakesh Kumar Kuncha
  • Metal Features to Reduce Crack-Inducing Stresses in Metallization Stacks
    Publication number: 20130087907
    Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bump structure above a first metallization layer of a metallization system of the semiconductor chip, and a metal feature in the first metallization layer, wherein at least a first portion of the metal feature is located closer to a center of the semiconductor chip than any portion of the bump structure, and at least a second portion of the metal feature is positioned below the bump structure.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Matthias U. Lehr, Holm Geisler, Frank Kuechenmeister