Abstract: The present invention relates to a method of performing collective die-to-wafer bonding. The method comprises the steps of: providing a carrier wafer having a back side and a bonding side opposite the back side and comprising on the bonding side one or more pockets that each are configured for accommodating a die, respectively, providing a target substrate comprising an integrated circuit, hereinafter IC, and one or more target bonding pads for connecting the one or more dies to the IC, placing one or more dies in the one or more pockets, respectively, and bonding the one or more dies placed in the one or more pockets to the tar-get substrate by bringing the one or more dies into contact with the one or more target bonding pads.

Abstract: A fan-out wafer-level package comprising at least one integrated circuit, an internal heat spreader thermally connected to the integrated circuit either directly or via an interface layer having a thickness in sub-?m range preferably in the range of 20 nm to 500 nm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.

Abstract: The invention relates to a method for annealing of at least two wafers bonded via low-temperature direct bonding comprising heating the bonded wafers up to a first annealing temperature in the range of 100° C. to 500° C., preferably 150° C. to 400° C., even more preferred 150° C. to 200° C., holding the first annealing temperature in a range of 1 to 4 hours, preferably 1 to 3 hours, cooling down the bonded wafers to room temperature, re-heating the bonded wafers to a second annealing temperature in the range of 100° C. to 500° C., preferably 150° C. to 400° C., even more preferred 150° C. to 200° C., and cooling down the bonded wafers to room temperature.

Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.

Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.