Abstract: A method or testing a system. Input parameters of the system are divided into a first group and a second group. Using a first method, a first selection is made from among the input parameter assignments of the first group. Using a second method, a second selection is made from among the input parameter assignments of the second group. A characteristic value is calculated from the second selection. The first selection is adapted depending on the characteristic value.

Abstract: Reducing the number of parameters in a visual parameter set based on a sensitivity analysis of how a given visual parameter affects the performance of a computer vision model to provide a verification parameter set having a reduced size.

Abstract: A computer-implemented method for training a computer vision model to characterise elements of observed scenes parameterized using visual parameters. During the iterative training of the computer vision model, the latent variables of the computer vision model are altered based upon a (global) sensitivity analysis used to rank the effect of visual parameters on the computer vision model.

Abstract: Facilitating the description or configuration of a computer vision model by generating a data structure comprising a plurality of language entities defining a semantic mapping of visual parameters to a visual parameter space based on a sensitivity analysis of the computer vision model.

Abstract: Modifying a visual parameter specification characterising the operational design domain of the computer vision model by improving the visual parameter specification according to a sensitivity analysis of the computer vision model.

Abstract: A computer-implemented method for ascertaining a closure point in time of an injector of an internal combustion engine using a classifier. The method includes: ascertaining a time series of input signals, each corresponding to a point in time within the time series, and each characterizing a deformation of the injector; ascertaining a plurality of first values using the classifier based on the time series, in each case a first value corresponding to a point in time of the time series, and the first value characterizing a probability that the closure point in time of the injector matches the point in time; ascertaining a plurality of second values, each being a sum of neighboring first values, of a first value and the first value, the second value corresponding to the point in time to which the first value corresponds; ascertaining the closure point in time based on the largest second value.

Abstract: A device and a computer-implemented method for machine learning. First input data are provided which encompass information concerning dimensions and options for the machine learning. At least one of the options is associated with at least one of the dimensions as a function of information concerning the dimensions and options for at least one test case for the machine learning. A combination of options for a subset of the dimensions that is lacking in the set of test cases is determined, and a test case is determined for this combination.

Abstract: A computer-implemented method for testing a vehicle system. In the method, data of a digital road map are read in, zones are determined for the digital road map, possible sequences of drives along a road of the digital road map are ascertained as a function of the determined zones, a behavior of the vehicle or of a vehicle system of the vehicle is ascertained in a simulation for at least one of the possible sequences, and it is determined as a function of a comparison of the ascertained behavior with at least one predetermined requirement whether the vehicle system exhibits an error or a weakness.

Abstract: A computer-implemented method for controlling a vehicle. The method includes: data of a digital road map are read in, zones are determined for the digital road map, possible sequences of drives along a road of the digital road map are ascertained as a function of the determined zones, a behavior of the vehicle or of a vehicle system of the vehicle is ascertained in a simulation for at least one of the possible sequences, and the vehicle is controlled in accordance with one of the possible sequences as a function of a comparison of the ascertained behavior with at least one predetermined requirement.

Abstract: A method or testing a system. Input parameters of the system are divided into a first group and a second group. Using a first method, a first selection is made from among the input parameter assignments of the first group. Using a second method, a second selection is made from among the input parameter assignments of the second group. A characteristic value is calculated from the second selection. The first selection is adapted depending on the characteristic value.

Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

Abstract: In a method for operating a motor vehicle, in particular a car, comprising an internal combustion engine, a vehicle battery and an occupant cell, the internal combustion engine being operated with a start/stop function wherein the internal combustion engine is switched on and off automatically during the operation of the vehicle in dependence on parameters such as a current drive power demand, and temperature, the start/stop function is activated only if the vehicle battery has a battery temperature which is above a minimum temperature value and the battery is exposed to the heated or cooled air conducted through the occupant cell of the vehicle.

Abstract: The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: Reduction of power consumption and chip area of a microprocessor employing speculative performance counting, comprising splitting a counter and a backup register of a speculative counting mechanism performing the speculative performance counting into first and second parts each, re-using an available storage within the microprocessor as first parts respectively; integrating at least one dedicated pre-counter into the microprocessor as second parts respectively; splitting the data handled by the speculative counting mechanism in high-order and low-order bits; storing the high order bits in the first parts; storing the low order bits in the second parts; updating the first parts periodically; and saving and propagating the carry-out from the second parts to high-order bits when a corresponding first part of the second parts is next updated respectively.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.