Patents by Inventor Matthieu Le Boulaire

Matthieu Le Boulaire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965566
    Abstract: System for suctioning braking particles from a friction braking system, the suction system including a negative-pressure source, a suction mouth, a pneumatic circuit connecting the suction mouth and the negative-pressure source, and a control unit, the suction system further including a closure unit arranged on the pneumatic circuit, the closure unit being able to isolate at least a first portion of the pneumatic circuit, the control unit being configured to control the closure means according to a predetermined logic in order to isolate the first portion of the pneumatic circuit during certain phases between two actual uses of the negative-pressure source.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 23, 2024
    Assignee: TALLANO TECHNOLOGIE
    Inventors: Loïc Adamczak, Thibaut Le Boulaire, Matthieu Hascoet
  • Patent number: 9092590
    Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 28, 2015
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SA
    Inventors: Bastien Giraud, Philippe Flatresse, Matthieu Le Boulaire, Jean-Philippe Noel
  • Publication number: 20140173544
    Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Inventors: Bastien Giraud, Philippe Flatresse, Matthieu Le Boulaire, Jean-Philippe Noel
  • Patent number: 8482070
    Abstract: An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: July 9, 2013
    Assignee: STMicroelectronics (Crolles 2)
    Inventors: Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Matthieu Le Boulaire