Patents by Inventor Matthieu Tuna

Matthieu Tuna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated method for analyzing a board having a plurality of FPGA components
    Patent number: 10120019
    Abstract: The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: November 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Matthieu Tuna, Zied Marrakchi, Christophe Alexandre
  • AUTOMATED METHOD FOR ANALYZING A BOARD HAVING A PLURALITY OF FPGA COMPONENTS
    Publication number: 20160161551
    Abstract: The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.
    Type: Application
    Filed: July 8, 2014
    Publication date: June 9, 2016
    Applicant: Mentor Graphics Corporation
    Inventors: Matthieu Tuna, Zied Marrakchi, Christophe Alexandre