Patents by Inventor Mattia Cichocki
Mattia Cichocki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230639Abstract: Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.Type: ApplicationFiled: March 28, 2023Publication date: July 20, 2023Inventors: Mattia CICHOCKI, Violante MOSCHIANO, Tommaso VALI, Guido Luciano RIZZO, Chang Wan HA, Richard FASTOW
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Publication number: 20230017305Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.Type: ApplicationFiled: April 27, 2022Publication date: January 19, 2023Inventors: Mattia Cichocki, Vladimir Mikhalev, Phani Bharadwaj Vanguri, James Eric Davis, Kenneth William Marr, Chiara Cerafogli, Michael James Irwin, Domenico Tuzi, Umberto Siciliani, Alessandro Alilla, Andrea Giovanni Xotta, Chung-Ping Wu, Luigi Marchese, Pasquale Conenna, Joonwoo Nam, Ishani Bhatt, Fulvio Rori, Andrea D'Alessandro, Michele Piccardi, Aleksey Prozapas, Luigi Pilolli, Violante Moschiano
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Patent number: 10134481Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state.Type: GrantFiled: March 3, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea D'Alessandro, Violante Moschiano, Mattia Cichocki, Michele Incarnati, Federica Paolini
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Patent number: 10037809Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: GrantFiled: October 2, 2017Date of Patent: July 31, 2018Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20180075913Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: ApplicationFiled: October 2, 2017Publication date: March 15, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20170345511Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state.Type: ApplicationFiled: March 3, 2017Publication date: November 30, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Andrea D'Alessandro, Violante Moschiano, Mattia Cichocki, Michele Incarnati, Federica Paolini
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Patent number: 9779826Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: GrantFiled: July 24, 2017Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Patent number: 9754674Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: GrantFiled: October 7, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Patent number: 9589659Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state.Type: GrantFiled: May 25, 2016Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Andrea D'Alessandro, Violante Moschiano, Mattia Cichocki, Michele Incarnati, Federica Paolini
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Publication number: 20170025181Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Patent number: 9502125Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: GrantFiled: September 8, 2014Date of Patent: November 22, 2016Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20160071605Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Patent number: 9093579Abstract: Pixel arrays are provided for image sensors that have barriers between color filters in an array of color filters. Color filter barriers may be formed from a transparent or semi-transparent material. Color filter barriers may be formed from a low refractive index material. Color filters may be etched and color filter barrier material may be formed in the etched regions of the color filters. If desired, a layer of color filter barrier material may be etched to form open regions and color filter material may be formed in the open regions of the color filter barrier material. An image sensor may be a front-side illuminated image sensor or a back-side illuminated image sensor.Type: GrantFiled: November 11, 2011Date of Patent: July 28, 2015Assignee: Semiconductor Components Industries, LLCInventors: Jeffrey Mackey, Ulrich Boettiger, Mattia Cichocki, Loriston Ford, Rick Holscher, Mitchell J. Mooney, Brian Vaartstra
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Patent number: 8372763Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.Type: GrantFiled: May 14, 2012Date of Patent: February 12, 2013Assignee: Aptina Imaging CorporationInventor: Mattia Cichocki
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Publication number: 20120273906Abstract: Pixel arrays are provided for image sensors that have barriers between color filters in an array of color filters. Color filter barriers may be formed from a transparent or semi-transparent material. Color filter barriers may be formed from a low refractive index material. Color filters may be etched and color filter barrier material may be formed in the etched regions of the color filters. If desired, a layer of color filter barrier material may be etched to form open regions and color filter material may be formed in the open regions of the color filter barrier material. An image sensor may be a front-side illuminated image sensor or a back-side illuminated image sensor.Type: ApplicationFiled: November 11, 2011Publication date: November 1, 2012Inventors: Jeffrey Mackey, Ulrich Boettiger, Mattia Cichocki, Loriston Ford, Rick Holscher, Mitchell J. Mooney, Brian Vaartstra
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Publication number: 20120225567Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Inventor: Mattia Cichocki
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Patent number: 8198731Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.Type: GrantFiled: February 20, 2009Date of Patent: June 12, 2012Assignee: Aptina Imaging CorporationInventor: Mattia Cichocki
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Publication number: 20100117240Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.Type: ApplicationFiled: February 20, 2009Publication date: May 13, 2010Inventor: Mattia Cichocki