Abstract: An apparatus includes processing hardware, storage hardware, and serial communication hardware. The processing hardware receives selection of a serial communication protocol. The serial communication protocol is selected amongst multiple serial communication protocols to control operation of a power converter. Via the processing hardware or other suitable entity, the storage hardware is populated with a set of command decode functions (a.k.a., command descriptors) assigned to the selected serial communication protocol. During operation, the serial communication hardware receives commands over a serial communication interface and executes the received commands via the set of command decode functions in the storage hardware. Each of the multiple commands communicated over the serial communication interface is encoded in accordance with the selected serial communication protocol. The serial communication hardware uses the set of command decode functions to execute the received commands.

Abstract: A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.

Abstract: A controller for a power converter includes: a first sense terminal and a second sense terminal for sensing an output voltage of the power converter; a bridging circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridging circuit in the first state during a portion of a voltage ramp of the power converter, and to determine whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit in the first state.

Abstract: A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate that one or more of the power stages is faulty and disabled; communicate the throttling signal to the processor over a physical line running between the processor and the controller; and place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: A controller for a power converter includes: a first sense terminal and a second sense terminal for sensing an output voltage of the power converter; a bridging circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridging circuit in the first state during a portion of a voltage ramp of the power converter, and to determine whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit in the first state.

Abstract: A multiphase voltage regulator includes a plurality of power stages, a plurality of current sense circuits, a controller and a current sense interface running between the controller and one or more of the current sense circuits. The current sense interface includes a separate line for each current sense circuit coupled to the current sense interface and which is configured to support single-ended or differential current sense. The regulator also includes a plurality of pullup circuits, each of which is connected to one of the current sense interface lines and has a higher impedance than the line to which it is connected. A fault detection circuit of the controller determines if an individual one of the current sense interface lines has an open fault, based on the pullup circuit connected to the line with the open fault pulling up the voltage on the line by more than a predetermined amount.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate that one or more of the power stages is faulty and disabled; communicate the throttling signal to the processor over a physical line running between the processor and the controller; and place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: A multiphase voltage regulator includes a plurality of power stages, a plurality of current sense circuits, a controller and a current sense interface running between the controller and one or more of the current sense circuits. The current sense interface includes a separate line for each current sense circuit coupled to the current sense interface and which is configured to support single-ended or differential current sense. The regulator also includes a plurality of pullup circuits, each of which is connected to one of the current sense interface lines and has a higher impedance than the line to which it is connected. A fault detection circuit of the controller determines if an individual one of the current sense interface lines has an open fault, based on the pullup circuit connected to the line with the open fault pulling up the voltage on the line by more than a predetermined amount.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate if one or more of the power stages is faulty and disabled; and communicate the throttling signal to the processor over a physical line running between the processor and the controller. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: A method of regulating an output voltage of a buck converter during a startup period in which the buck converter is first enabled includes regulating the output voltage of the buck converter to a reference voltage under current-mode control during a first part of the startup period, and regulating the output voltage of the buck converter to the reference voltage under voltage-mode control during a second, later part of the startup period. The reference voltage ramps up from an initial voltage at the beginning of the startup period to a target voltage at the end of the startup period. Buck converter embodiments are also described.

Abstract: A method of regulating an output voltage of a buck converter during a startup period in which the buck converter is first enabled includes regulating the output voltage of the buck converter to a reference voltage under current-mode control during a first part of the startup period, and regulating the output voltage of the buck converter to the reference voltage under voltage-mode control during a second, later part of the startup period. The reference voltage ramps up from an initial voltage at the beginning of the startup period to a target voltage at the end of the startup period. Buck converter embodiments are also described.

Abstract: The present invention relates to a high-speed interface for radio systems, in particular to a synchronous serial digital interface for a car radio. In an embodiment, the synchronous serial digital interface for at least dual radio receiver systems includes a master device and a slave device. The dual radio receiver system has an intermediate frequency. The master device and the slave device exchange data in a bi-directional manner on at least one communication channel; the master device and the slave device have a unique bit clock; the master device supplies a synchronization signal to the slave device. The synchronization signal has a frequency spectrum with an amplitude at the intermediate frequency lower than the amplitudes at the other frequencies of the synchronization signal.

Abstract: The present invention relates to a high-speed interface for radio systems, in particular to a synchronous serial digital interface for car radio. In an its embodiment the synchronous serial digital interface for at least dual radio receiver systems comprises a master device and a slave device; the dual radio receiver systems having an intermediate frequency; the master device and the slave device exchange data in bi-directional manner on at least one communication channel; the master device and the slave device have a unique bit clock; the master device supply a synchronization signal to the slave device the synchronization signal has a frequency spectrum with an amplitude at the intermediate frequency lower than the amplitude of other frequencies.