Patents by Inventor Mattias A. Hembruch

Mattias A. Hembruch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit partitioning and timing
    Patent number: 9026974
    Abstract: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: May 5, 2015
    Assignee: Synopsys, Inc.
    Inventors: Russell B. Segal, Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch
  • WHAT-IF PARTITIONING AND TIMING
    Publication number: 20140181776
    Abstract: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 26, 2014
    Applicant: Synopsys, Inc.
    Inventors: Russell B. Segal, Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch