Abstract: This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.

Abstract: This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.

Abstract: This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.

Abstract: This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.

Abstract: A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.

Abstract: According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.

Abstract: A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.

Abstract: According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.

Abstract: A method, computer program product, and data processing system for efficiently storing a set of hierarchically-specified names in a modular hardware design are disclosed. In accordance with a preferred embodiment of the present invention, a data structure for storing the names is built from a master trie. The master trie is used to store names of instances of modules contained within the design. The node in the master trie corresponding to a particular instance name is associated with an additional trie (“class trie”) corresponding to the class of module to which that instance belongs. In this additional trie are stored the names of the individual signals associated with that class of module. Where there are multiple instances of the same class of module within a design, each instance name may be associated with a single class trie storing each of the individual signal names associated with that class of module.

Abstract: According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.