Patents by Inventor Mau-Lin Wu
Mau-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220239331Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
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Patent number: 11329691Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.Type: GrantFiled: June 24, 2020Date of Patent: May 10, 2022Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
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Publication number: 20200321999Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.Type: ApplicationFiled: June 24, 2020Publication date: October 8, 2020Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
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Patent number: 10727897Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.Type: GrantFiled: August 10, 2017Date of Patent: July 28, 2020Assignee: MediaTek Inc.Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
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Publication number: 20180048348Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.Type: ApplicationFiled: August 10, 2017Publication date: February 15, 2018Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
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Publication number: 20150341158Abstract: A loop gain calibration apparatus has an exciting signal generator, an exciting signal extracting circuit, and a loop gain control circuit. The exciting signal generator generates a first exciting signal and injects the first exciting signal into a timing recovery loop while the timing recovery loop is operating in response to a reception signal received under a normal reception mode. The exciting signal extracting circuit extracts a second exciting signal from the timing recovery loop after the first exciting signal is injected into the timing recovery loop. The loop gain control circuit receives the first exciting signal from the exciting signal generator, receives the second exciting signal from the exciting signal extracting circuit, and controls a loop gain of the timing recovery loop according to the first exciting signal and the second exciting signal.Type: ApplicationFiled: May 8, 2015Publication date: November 26, 2015Inventors: Kuo-Ming Wu, Ching-Shyang Maa, Shu-Hsien Wang, Chung-Jung Huang, Guo-Hau Gau, Mau-Lin Wu
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Publication number: 20090285315Abstract: An apparatus and a method for adaptive channel estimation and a coherent bandwidth estimation apparatus are provided. The adaptive channel estimation apparatus includes a first channel estimator, a coherent bandwidth estimator and a second channel estimator. The first channel estimator uses a predetermined approach to calculate a first channel response of each tone of an orthogonal frequency-division multiplexing (OFDM) signal. The coherent bandwidth estimator is coupled to the first channel estimator for calculating a coherent bandwidth according to the first channel responses. The second channel estimator is coupled to the first channel estimator and the coherent bandwidth estimator. For each of the tones, the second channel estimator calculates a weighted average according to the coherent bandwidth and the first channel responses of several adjacent tones including the aforementioned tone. The second channel estimator outputs the weighted average as the second channel response of the aforementioned tone.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventor: Mau-Lin Wu
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Publication number: 20090122890Abstract: An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system.Type: ApplicationFiled: November 8, 2007Publication date: May 14, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventor: Mau-Lin Wu
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Publication number: 20090003385Abstract: In a wireless communication method and system, a data/pilot constellation is modulated and generated based on input information bits. Channel estimation (CE) sequence in frequency-domain is off-line generated. The frequency-domain channel estimation sequence is transformed into a time-domain channel estimation sequence by ideal IFFT to avoid IFFT (Inverse Fast Fourier Transform) impact to EVM (Error Vector Magnitude) performance. Off-line resealing the time-domain CE sequence, multiplied by a rescaling coefficient, in time-domain improves EVM performance. Further, the time-domain channel estimation sequence is off-line quantized.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventor: Mau-Lin Wu
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Patent number: 7424664Abstract: A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.Type: GrantFiled: October 17, 2005Date of Patent: September 9, 2008Assignee: Faraday Technology Corp.Inventor: Mau-Lin Wu
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Patent number: 7369630Abstract: A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.Type: GrantFiled: November 29, 2004Date of Patent: May 6, 2008Assignee: Faraday Technology Corp.Inventor: Mau-Lin Wu
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Publication number: 20070286221Abstract: A memory management method and a memory architecture for transmitting ultra-wideband (UWB) prioritized channel access (PCA) frames are provided. The method comprises the steps of assigning a pre-load queue to each of a plurality of access categories for storing UWB PCA frames to be transmitted, and, when one of the access categories gains transmission opportunity (TXOP), assigning a common area queue to that access category for storing UWB PCA frames to be transmitted. Moreover, when a UWB PCA frame in one of the pre-load queues reaches a predetermined size, the access category corresponding to the pre-load queue starts its backoff state machine in order to gain the TXOP.Type: ApplicationFiled: June 13, 2006Publication date: December 13, 2007Inventors: Mau-Lin Wu, Tung-Hui Lee, Chieh-Hua Chen, Hsin-Pu Chung, Youn-Tai Lee
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Patent number: 7283926Abstract: Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.Type: GrantFiled: October 24, 2005Date of Patent: October 16, 2007Assignee: Faraday Technology Corp.Inventor: Mau-Lin Wu
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Publication number: 20070093984Abstract: Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventor: Mau-Lin Wu
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Publication number: 20070089041Abstract: A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.Type: ApplicationFiled: October 17, 2005Publication date: April 19, 2007Inventor: Mau-Lin Wu
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Publication number: 20060115024Abstract: A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying “PAD” to replace “PCD” into “pre-selection” subgroups with “max-and-zero” property, the invention can reduce the implementation cost without performance degradation.Type: ApplicationFiled: November 29, 2004Publication date: June 1, 2006Inventor: Mau-Lin Wu
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Patent number: 6912109Abstract: A new ESD (Electrostatic Discharge) protection circuit with well-triggered PMOS is provided for application in power-rail ESD protection. A PMOS device is connected between the VDD and VSS power lines to sustain the ESD overstress current during the time that the ESD voltage is applied between the VDD and the VSS power lines. In deep submicron CMOS p-substrate technology, the weak point of ESD overstress control is typically associated with the NMOS device. For this reason, the invention uses a power-rail ESD clamp circuit that incorporates a PMOS device. Applying gate-coupled and N-well triggering techniques, the PMOS can be turned on more efficiently when the ESD overstress is present between the power lines. For p-substrate CMOS technology, it is difficult to couple a high voltage to the substrate of the NMOS device while high voltage is readily coupled to the N-well of a PMOS device. The proposed ESD clamp circuit can be applied efficiently to protect the ESD overstress between power rails.Type: GrantFiled: June 26, 2000Date of Patent: June 28, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Dou Ker, Mau-Lin Wu
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Patent number: 6750517Abstract: A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.Type: GrantFiled: November 6, 2000Date of Patent: June 15, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ming-Dou Ker, Mau-Lin Wu
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Patent number: 6414532Abstract: An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.Type: GrantFiled: September 27, 2001Date of Patent: July 2, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung Der Su, Jian-Hsing Lee, Yi-Hsun Wu, Mau-Lin Wu