Patents by Inventor Mau-Phon Houng

Mau-Phon Houng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7439091
    Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is deposed on the first surface of the illuminant epitaxial structure. A metal layer is formed on the second surface of the illuminant epitaxial structure. An anodic oxidization step is performed to oxidize the metal layer, so as to form a metal oxide layer. An etching step is performed to remove a portion of the metal oxide layer, so as to form a plurality of holes in the metal oxide layer.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: October 21, 2008
    Assignee: Epistar Corporation
    Inventors: Shi-Ming Chen, Mau-Phon Houng, Chang-Hsing Chu, Te-Chi Yen
  • Publication number: 20070221927
    Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is deposed on the first surface of the illuminant epitaxial structure. A metal layer is formed on the second surface of the illuminant epitaxial structure. An anodic oxidization step is performed to oxidize the metal layer, so as to form a metal oxide layer. An etching step is performed to remove a portion of the metal oxide layer, so as to form a plurality of holes in the metal oxide layer.
    Type: Application
    Filed: February 22, 2007
    Publication date: September 27, 2007
    Applicant: Epitech Technology Corporation
    Inventors: Shi-Ming Chen, Mau-Phon Houng, Chang-Hsing Chu, Te-Chi Yen
  • Patent number: 6689645
    Abstract: In the fabrication of gate oxides in IC process, a suitable cleaning/etching process is required to remove the native oxides and reduce surface microroughness in addition to standard RCA cleaning. For ultrathin oxide thickness (<10 nm), it is an important issue to have a native-oxide-free and H-passivated silicon (Si) surface to ensure high breakdown field, high charge-to-breakdown, and low leakage current. According to these concepts, we propose an invention with a simple two-step hydrogen fluoride (HF) etching process to improve the electrical properties of liquid-phase deposited fluorinated silicon oxides (LPD-SiOF), including effective removal of native oxides, lowering of interface trap density (˜1010 eV−1 cm−2), reduction of surface microroughness (Ra=0.1 nm), and raising of breakdown field (˜9.7 MV/cm). Furthermore, rapid thermal annealing (RTA) is also used to further improve the oxide quality.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: February 10, 2004
    Assignee: National Science Council
    Inventors: Mau-Phon Houng, Yeong-Her Wang, Wai-Jyh Chang
  • Publication number: 20020102775
    Abstract: In the fabrication of gate oxides in IC process, a suitable cleaning/etching process is required to remove the native oxides and reduce surface microroughness in addition to standard RCA cleaning. For ultrathin oxide thickness (<10 nm), it is an important issue to have a native-oxide-free and H-passivated silicon (Si) surface to ensure high breakdown field, high charge-to-breakdown, and low leakage current. According to these concepts, we propose an invention with a simple two-step hydrogen fluoride (HF) etching process to improve the electrical properties of liquid-phase deposited fluorinated silicon oxides (LPD-SiOF), including effective removal of native oxides, lowering of interface trap density (˜1010 eV−1 cm−2), reduction of surface microroughness (Ra=0.1 nm), and raising of breakdown field (˜9.7 MV/cm). Furthermore, rapid thermal annealing (RTA) is also used to further improve the oxide quality.
    Type: Application
    Filed: May 10, 2001
    Publication date: August 1, 2002
    Inventors: Mau-Phon Houng, Yeong-Her Wang, Wai-Jyh Chang
  • Publication number: 20020094699
    Abstract: A method of fabricating a MOSEFT device, which is suitable for fabricating an III-V group semiconductor device. A substrate comprises a buffer layer and a channel layer, wherein silicon oxide is formed on the channel layer by a liquid phase deposition method (LPD) to control the parameters of growth solution. A silicon oxide insulating layer that is formed on the channel layer has a thickness of approximately 40 Å, wherein the silicon oxide insulating layer is used as a gate oxide layer. A source, a drain and a gate are formed on the gate oxide layer. The LPD process is performed in a temperature range from room temperature to 60° C. Thus, the low temperature of the LPD technique will not lead to a negative heat effect on other fabrications or on the wafer, therefore the low temperature will not cause thermal stress, dopant redistribution, dopant diffusion or material interaction, for example.
    Type: Application
    Filed: January 12, 2001
    Publication date: July 18, 2002
    Inventors: Mau-Phon Houng, Yeong-Her Wang, Zhen-Song Ya
  • Patent number: 6326317
    Abstract: Disclosed is a method for manufacturing a metal oxide semiconductor FET (MOSFET), which utilizes a low-temperature liquid phase oxidation for III-V group. The method includes the steps of (a) providing a substrate, (b) forming an epitaxial layer on the substrate, (c) defining and forming a drain and a source on a portion of the epitaxial layer, (d) forming a recess in an another portion of the epitaxial layer, (e) forming an oxide layer on a surface of the recess by relatively low-temperature oxidation, and (f) forming a gate on a portion of the oxide layer between the drain and source. In addition, the method further includes two selective procedures, that is, a synchronic sulfurated passivation process which can be performed with the growth of the oxide film simultaneously, and a rapid thermal annealing (RTA) process.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: December 4, 2001
    Assignee: National Science Council
    Inventors: Hwei-Heng Wang, Yeong-Her Wang, Mau-Phon Houng
  • Patent number: 6004886
    Abstract: A method for growing a silicon dioxide film on a HgCdTe substrate includes a first step in which the HgCdTe substrate is cleaned with an alkaline aqueous solution. The cleaned HgCdTe substrate is then dried before being immersed in a liquid phase deposition solution in which the silicon dioxide film is deposited on the surface of the HgCdTe substrate at the rate as high as 1672 .ANG./hr. The silicon dioxide film has a refraction rate as high as 1.465.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: December 21, 1999
    Assignee: National Science Council
    Inventors: Mau-Phon Houng, Yeong-Her Wang, Na-Fu Wang
  • Patent number: 5998304
    Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: December 7, 1999
    Assignee: National Science Council
    Inventors: Mau-Phon Houng, Yeong-Her Wang, Chien-Jung Huang
  • Patent number: 5958519
    Abstract: A method is provided for forming an oxide film on a III-V substrate. The method includes steps of (a) preparing an acidic solution containing a IIIA-ion, (b) adding an basic solution into the acidic solution to provide a growth solution of a specific pH value, and (c) placing the III-V substrate into the growth solution to form the oxide film on the III-V substrate.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: September 28, 1999
    Assignee: National Science Council
    Inventors: Hwei-Heng Wang, Yeong-Her Wang, Mau-Phon Houng