Patents by Inventor Maung H. Kyaw

Maung H. Kyaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6482719
    Abstract: An MOS device is provided having a channel-stop implant placed between active regions and beneath field oxides. The channel-stop dopant material is a p-type material of atomic weight greater than boron, and preferably utilizes solely indium ions. The indium ions, once implanted, have a greater tendency to remain in their position than boron ions. Subsequent temperature cycles caused by, for example, field oxide growth do not significantly change the initial implant position. Thus, NMOS devices utilizing indium channel-stop dopant can achieve higher pn junction breakdown voltages and lower parasitic source/drain-to-substrate capacitances. Furthermore, the heavier indium ions can be more accurately placed than lighter boron ions to a region just below the silicon layer which is to be consumed by subsequent field oxide growth. By fixing the peak concentration density of indium at a depth just below the field oxide lower surface, channel-stop implant region is very shallow.
    Type: Grant
    Filed: August 2, 1995
    Date of Patent: November 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohammed Anjum, Alan L. Stuber, Maung H. Kyaw
  • Patent number: 5593907
    Abstract: A semiconductor structure with large tile angle boron implant is provided for reducing threshold shifts or rolloff at the channel edges. By minimizing threshold shifts, short channel effects and subthreshold currents at or near the substrate surface are lessened. The semiconductor structure is prepared by implanting boron at a non-perpendicular into the juncture between the channel and the source/drain as well as the juncture between the field areas and the source/drain. Placement of boron into these critical regions replenishes segregating and redistributing threshold adjust implant species and channel stop implant species resulting from process temperature cycles. Using lighter boron ions allow for a lesser annealing temperature and thereby avoids the disadvantages of enhanced redistribution and diffusion caused by high temperature anneal.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: January 14, 1997
    Assignee: Advanced Micro Devices
    Inventors: Mohammed Anjum, Klaus H. Koop, Maung H. Kyaw
  • Patent number: 5471293
    Abstract: A method and device is provided for determining defects within a single crystal substrate. The methodology includes a surface photovoltage (SPV) technique in which the magnitude of non-linearity is quantified and correlated to defects within the crystal lattice. The correlation factor is determined in a rapid and efficient manner using least square correlation methodology without having to determine diffusion length and incur difficulties associated therewith. Obtaining a quantifiable least square correlation factor allows the operator to quickly determine the amount of crystalline damage often encountered by, for example, ion implantation. In addition, the operator can determine the relative depth and position of defective crystalline layers within the substrate based upon demarcations between monotonically and non-monotonically aligned points plotted in a graph of reciprocal photovoltage versus reciprocal absorption coefficient.
    Type: Grant
    Filed: February 2, 1994
    Date of Patent: November 28, 1995
    Assignee: Advanced Micro Devices
    Inventors: John K. Lowell, Mohammed Anjum, Valerie A. Wenner, Norman L. Armour, Maung H. Kyaw
  • Patent number: 5429972
    Abstract: An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: July 4, 1995
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohammed Anjum, Klaus H. Koop, Maung H. Kyaw
  • Patent number: 5360749
    Abstract: A semiconductor structure with germanium implant is provided for reducing V.sub.T shifts at the channel edges thereby minimizing short channel effects and subthreshold currents at or near the substrate surface. The semiconductor structure is adapted to receive non-perpendicular implant of germanium in the juncture between the channel and the source/drain regions as well as in the juncture between field oxide channel stop implant and source/drain regions. By carefully and controllably placing the germanium at select channel and field regions, segregation and redistribution of threshold adjust implant and channel stop implant dopant materials is substantially minimized. Reducing the redistribution of such materials provides a reduction in the short channel effects and, particularly, a reduction in substrate surface current or DIBL-induced current.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: November 1, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohammed Anjum, Klaus H. Koop, Maung H. Kyaw