Patents by Inventor Maureen Brongo

Maureen Brongo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7109125
    Abstract: Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is exposed to a dielectric conversion source such as E-beams, I-beams, oxygen plasma, or an appropriate chemical. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of capacitor trenches are etched in the second area of the dielectric. The capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area. In another embodiment, the exposure to the dielectric conversion source is not performed until after the chemical mechanical polish has been performed.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: September 19, 2006
    Assignee: Newport Fab, LLC
    Inventors: Q. Z. Liu, David Feiler, Bin Zhao, Phil N. Sherman, Maureen Brongo
  • Patent number: 7049246
    Abstract: Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered while a second area of the dielectric layer is exposed to a dielectric conversion source. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of interconnect trenches are etched in the first area of the dielectric and a number of capacitor trenches are etched in the second area of the dielectric. The interconnect trenches and the capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: May 23, 2006
    Assignee: Newport Fab, LLC
    Inventors: Q. Z. Liu, David Feiler, Bin Zhao, Phil N. Sherman, Maureen Brongo
  • Patent number: 6709564
    Abstract: The acid copper sulfate solutions used for electroplating copper circuitry in trenches and vias in IC dielectric material in the Damascene process are replaced with a type of plating system based on the use of highly complexing anions (e.g., pyrophosphate, cyanide, sulfamate, etc.) to provide an inherently high overvoltage that effectively suppresses runaway copper deposition. Such systems, requiring only one easily-controlled organic additive species to provide outstanding leveling, are more efficacous for bottom-up filling of Damascene trenches and vias than acid copper sulfate baths, which require a minimum of two organic additive species. The highly complexed baths produce fine-grained copper deposits that are typically much harder than large-grained acid sulfate copper deposits, and which exhibit stable mechanical properties that do not change with time, thereby minimizing “dishing” and giving more consistent CMP results.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: March 23, 2004
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: D. Morgan Tench, John T. White, Dieter Dornisch, Maureen Brongo