Patents by Inventor Maureen Hanratty

Maureen Hanratty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor having improved gate structure
    Patent number: 6753559
    Abstract: A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: June 22, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Wei William Lee, Greg A. Hames, Qizhi He, Maureen Hanratty, Iqbal Ali
  • Transistor having an improved gate structure and method of construction
    Patent number: 6436746
    Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: August 20, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Wei William Lee, Greg A. Hames, Qizhi He, Maureen Hanratty, Iqbal Ali
  • Transistor having improved gate structure
    Publication number: 20010046760
    Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).
    Type: Application
    Filed: July 6, 2001
    Publication date: November 29, 2001
    Inventors: Amitava Chatterjee, Wei William Lee, Greg A. Hames, Qizhi He, Maureen Hanratty, Iqbal Ali