Abstract: In 3D NAND type memory structures, such as of the BiCS type, the NAND strings have a channel that runs vertically up from the substrate between the memory cells and select gates. In an erase process, holes travel up from the well down at the substrate up towards the bit line in order to reach the cells to be erased. In such a process, the voltage applied to source side select gates should be low enough for the holes to pass through theses gates and up the column, but not so low as to result in device breakdown as the erase voltage is applied to the well. Techniques are presented to do this by controlling the source side select gate voltages so that the difference from the well voltage is kept largely constant during the erase process by use of a fixed offset during ramping and at the final level for the erase process.