Abstract: The present invention discloses a method and a system for performing fast division using non linear interpolation. A storage stores x-axis and y-axis coordinates (X0, Y0) of a plurality of non uniform interpolation points, and x-axis and y-axis coordinates (&Dgr;X, &Dgr;Y) representing the differences between two successive points of the plurality of non uniform interpolation points is used. The plurality of non uniform interpolation points is selected such that the x-axis difference (&Dgr;X) is a power n of 2 in the form of (&Dgr;X=2n), with n being an integer. Upon reception of an input operand X, the storage selects and outputs a set of coordinates (X0, &Dgr;Y, n, Y0) associated to the input operand.

Abstract: A network node supports switching fixed length information cells between a source unit and a destination unit. The invention uses two lookup tables called the active and the standby calendars for each of said output line. Each entry in the calendars represents the position of one cell in the output cell stream which will be sent onto said output lines. While the active calendar is controlling the network cell multiplexing onto a node output line, the standby calendar is updated at each traffic change by looking for a calendar free position for the new traffic starting with a targeted theoretical entry position. A Free Location Table (700) is used, storing the calendar organized by pages. The standby calendar updating starts with reading a Free Location Table page pointed at by the most significant bits of the theoretical entry. Should said page contain only ones (i.e., no free cell position) looking for the nearest page containing at least one zero (i.e.

Abstract: A protocol adapter for an Asynchronous Transfer Mode (ATM) cell switching system has a receive part and a transmit part, the receive part being arranged to convert an incoming ATM cell into a cell structured with a payload and a header including an output index (OI). The transmit part is arranged to convert the structured cell after it is routed through the switching system into an ATM cell, and to output the ATM cell on the ATM communication lines. The transmit part has cell processing logic for adding a bit (mother-bit) in the header of each incoming structured The output index of a mother cell is used to access a location in a look-up table which contains for each output index, a multicast bit for indicating whether the cell is to be multicasted or not, a queue index for indicating a location where to enqueue the cell before it is outputted from the transmit part, a new VP/VC/Li value for constructing a new header, and a next-output index.

Abstract: Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive pulse coded modulation (PCM) output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing one adder running three times faster than the sigma-delta clock for loading one of three accumulators. As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order in which the accumulators are loaded by the adder each PCM sampling time enables having zero as the last coefficient value to add to the accumulator, the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation.

Abstract: Data multiplexing system for dispatching an input serial bit stream onto a plurality of ports, or multiplexing the data bits received from a plurality of ports as a serial bit stream. The system mainly comprises for each port, a mask register (14) loaded with a N-bit mask work wherein bits set to 1 indicate which bits of an aggregate register (10 or 56) are to be loaded or to be transferred, and a scan counter (20 or 46) starting being incremented at a high frequency at each transition of a first category, up or down, of a clock circuit (12 or 40), until the mask bit corresponding to the scan counter contents is a bit 1, whereby the corresponding cell of the aggregate register is transmitted to the associated port or loaded with the bit received at this time by the associated port.

Abstract: An offset correction circuit is disclosed in a digital-to-analog coder (10) comprising a delta coder (18) providing a serial bit string at a high frequency F in response to digital words supplied at a low frequency F, and an analog integrator (22) providing an analog output signal (24) which is an analog representation of the digital words. The offset correction circuit avoids introducing an offset in the analog output of the integrator (22) when a PLO correction is taken to slow down or to speed up the clock controlling the input of the digital words. Such a circuit is implemented by a state generator which provides a corrected pulse in place of the sigma-delta data which lasts half the duration of the offset.

Abstract: A phase-locked clock incorporating a combined phase comparator and control device (20) that controls a multiplexer (22). Multiplexer (22) receives as inputs the outputs from circuits called decoders which add a predetermined digital value to, or subtract said value from, the value applied to the inputs thereof, which latter value is received from a buffer register (30) disposed at the output of the multiplexer. The contents of the buffer register are transferred under the control of a local oscillator (10). The output from the buffer register is fed to a fixed frequency divider (13) through a carry logic circuit (32).

Abstract: A programmable logic array which uses random-access memories to replace read only memories conventionally used in programmable logic arrays. The programmable logic array includes input and output terminals, an input register connected to the input terminals, an output register connected to the output terminals, first and second random-access memories, addressing means for sequentially and cyclically reading the random-access memories, a buffer register having an input to the output of the second random-access memory and an output connected to the input of the output register, a comparator having a first input connected to the output of the first random-access memory and a second input connected to the output of the input and output registers, the output of the comparator controlling the transfer of the contents of the buffer register and means for resetting the buffer register.

Abstract: A programmable logic array (PLA) is provided with a plurality of storage registers. The PLA includes an AND matrix which generates inputs to an OR matrix which in turn selectively feeds output signals into the storage registers. At a selected time, a selected storage register provides the output signals of the PLA and/or feedback signals to the AND array so that sequential logic functions can be performed in the PLA. The plurality of storage registers are used to store various combinations of the OR matrix output signals. A decoder permits selection of one of the registers at a time to allow time discrimination among the various stored combinations of the OR matrix output signals for the purposes of feeding them out of the PLA and/or feeding them back into the AND matrix.