Abstract: In a data processing system in which an extender unit interconnects the parallel bus of a control unit and a serial link of an extender channel, the channel and the extender unit send and receive serial frames that permit the extender unit to operate under the protocol of the parallel bus with either byte mode devices or non-byte mode devices. The control unit can be modified to operate with a byte mode device in data streaming, a high speed data transfer mode.

Abstract: In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the data channel. In addition, a transition bit is stored in each memory location to signify whether the vector information in that location represents valid transition data. The transition bit is used to control the reading of information from the memory into a register that controls the flow of information in the data channel, so that only the valid transition vectors are fed into data channel control circuitry. This procedure substantially reduces the amount of data that must be loaded into the memory, and hence reduces the total time necessary to thoroughly test a circuit.