Abstract: A process for manufacturing 2-isobutyl-6-(3-(methylamino)azetidin-1-yl)pyrimidin-4-amine of Formula (I): including starting from 6-chloro-2-isobutylpyrimidin-4-amine and tert-butyl azetidin-3-yl(methyl)carbamate, or another N-protected N-methylazetidin-3-amine, and performing the following steps: (a) coupling reaction of both compounds in dimethylsulfoxide in presence of potassium carbonate to afford an intermediate protected compound; and (b) deprotection of the protected compound to afford 2-isobutyl-6-(3-(methylamino)azetidin-1-yl)pyrimidin-4-amine. Also, a process for manufacturing the intermediate protected compound, wherein deprotection step (b) is omitted, and the compounds obtained from the processes.

Abstract: A process for manufacturing 2-isobutyl-6-(3-(methylamino)azetidin-l-yl)pyrimidin-4-amine of Formula (I): including starting from 6-chloro-2-isobutylpyrimidin-4-amine and tert-butyl azetidin-3-yl(methyl)carbamate, or another N-protected N-methylazetidin-3-amine, and performing the following steps: (a) coupling reaction of both compounds in dimethylsulfoxide in presence of potassium carbonate to afford an intermediate protected compound; and (b) deprotection of the protected compound to afford 2-isobutyl-6-(3-(methylamino)azetidin-1-yl)pyrimidin-4-amine. Also, a process for manufacturing the intermediate protected compound, wherein deprotection step (b) is omitted, and the compounds obtained from the processes.

Abstract: The invention relates to microfluidic systems, and more specifically to a microfluidic system comprising a capillary channel (14) and an inlet (12) for receiving a fluid, as well as a method of filling a capillary channel (14). Provided is a microfluidic system, having an inlet (12) for receiving a fluid, a capillary channel (14), an outlet (20) for letting excess fluid out, and a reservoir (10) for interfacing the inlet (12) to the capillary channel (14). The reservoir (10) forms a first passage from the inlet (12) to the outlet (20), and a second passage from the inlet (12) to an entrance (22) of the capillary channel (14). A hydraulic resistance of the first passage is sufficiently low in order to effect a pressure reduction at the entrance (22) of the capillary channel (14) when a fluid is received under pressure at the inlet (12).

Abstract: A data processing system is presented, comprising at least one central unit (CPU), at least one central memory (MMU), and internal communication bus to which the CPU and MMU are connected, at least one peripheral unit, a control module (IOM), and an external communication bus to which the peripheral unit and the control module are connected. In this system, the IOM is also connected to the internal communication bus. The internal and external communication buses are of differing types. Within the IOM, the connection to the internal communication bus is via an internal interface device (CLM), while the connection to the external communication bus is via an external interface device (PLM). An inter-device interface (PLI), also within the IOM, connects the CLM and PLM, so as to adapt the protocols of each to the other.

Abstract: A method of transmitting information in the form of electrical signals over a bidirectional link including a central station (S. C.) and a peripheral station (S. P.) connected to the central station via a bidirectional transmission bus (10), where the central station (S. C.) is provided with a clock (14) furnishing a synchronizing signal to the peripheral station (S. P.) is proposed, the method being characterized in that the synchronization is effected in the biphase mode upon transmission from the central station (S. C.), and in the monophase mode upon transmission from the peripheral station (S. P.). The invention is applicable to data transmission over a bidirectional link between various subsystems of a data processing system. The invention also relates to an apparatus for performing the above method.

Abstract: The invention describes an interface device for controlling data exchanges between a central unit and a plurality of satellite units each having an operative cycle of its own, without any chronometric relation imposed to the said units. Said interface device comprises an addressable arrangement memorizing a record of the timed sequence of the steps of each one of the operative cycles of the satellite units and an executer circuit which, on request from the central unit, sequentially scans the record of the operative cycle of the addressed satellite unit and applies to a command input of the said unit the actuation commands derived therefrom at an asynchronous timing of the steps of the said operative cycle record.

Abstract: A microprogram controlled operator device is described which processes bytes each of which is comprised of an equal number of binary-coded decimal figures. The device comprises first and second byte stores each of a multi-byte capacity, a logical and arithmetical operator circuit having inputs connected to read-out outputs of said stores and having an output to a buffer register and code handling organization, preferably further enabling "raw" byte inputting. An output of the code handling organization is connected to an input of a byte code processing arrangement which includes a multiplexer circuit having outputs to write-in inputs of the first and second stores and having further inputs connected to external data supplying means and to read-out outputs from the said stores. The organization further has an output to the external equipment wherein said device is connected.

Abstract: A field selection data operating device consists of three cascade connected circuits: a field selector and shifter circuit, an arithmetical and logical operator circuit and a bit shifter and concatenator circuit. The selector and shifter circuit is controlled by a field length code, a shift value code and a first field bit rank code. It comprises two stages of multiplexing members. The first stage ensures, in circular permutation, a shift of the bytes of an applied data word so as to place the byte containing the bit of the first field bit rank code at the place in the word pointed by the shift value code and the second stage completes the shift to the said bit in the byte and generates an output mask according to the field length code. The mask is also applied to concatenation control inputs of the bit shifter and concatenator circuit.

Abstract: An equipment for execution of maintenance operations in a multi-unit processing system one of which is a central unit comprises, in each unit, shift registers each made of a hardware series connection of multi-bit and single-bit register members which are parts of the unit and which, for part of them, copy the conditions of parts of the unit, and a local automaton for actuation and control of said shift registers, and a common maintenance station having command and data exchange facilities with the said local automatons. Each local automaton includes means responsive to local and remote commands for controlling read-out and write-in operations of said shift registers, interrupts of the operation of the unit and test and diagnosis routine executions by the said unit from the data in the said shift registers.

Abstract: An addressing device is described for a control store comprised of a read-only storage portion and a read-write storage portion, each divided in addressable microprogram sectors and both accessible through a common address register and accessing to a common read-out register. Said control store is a part of a multimicroprogrammed unit further comprising a logical unit, a status register for said logical unit and an automatic store address forming organization operating on data supplied from the common read-out register and the logical unit. When a microprogram stored in a sector of the read-write storage portion must be substituted for a microprogram stored in a sector of the read-only storage portion, the logical unit forces into the status register, a pointer code and the sector addresses of the concerned read-only and read-write storage portions.

Abstract: A supervising device is described for detecting errors in an automatic progression of the addresses of words which must be sequentially read out from a store under the control of a command logic forming the starting address from an operation code and thereafter incrementing the address by combining a portion of each read-out word with other data. Said device comprises a code comparator the output of which is activated when a code of a restricted number of bits derived from the operation code and a code of the same number of bits derived from a read out word disagree except when this second code presents a particular configuration of bits as, for instance an all identical binary value bit configuration.