Abstract: The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.

Abstract: A sampling device for sampling an input signal in response to a pulse train of a sample signal. The sampling device includes a sampling transistor for creating samples in response to the sample signal. The sampling transistor has an impedance corresponding with the difference between the gate to source voltage and the threshold voltage of the sampling transistor. The sampling device also includes a control device for generating a control signal. The control device includes a bootstrap reference voltage source for providing a reference voltage in response to the sample signal, and a control circuit for generating the control circuit voltage in response to the sample signal. By this design, the control signal comprises the sum of the input signal and the sampling threshold voltage, the control signal comprises the sum of control circuit voltage and the reference voltage, and the gate to source voltage comprises the difference between the control signal and the input signal.

Abstract: A high speed and low power digital circuit for producing an output responsive to a plurality of input data signals, such as a multiplexer or a latch includes one or more data switching elements. Each of the switching elements is a differential transistor pair having one transistor driven by a control signal and the other transistor driven by a data signal. The signal levels for the data and control signals are interleaved so that each control signal turns on and off the effect of the data signal on the current flow in the switching element. The circuit structure avoids emitter coupling more than two transistors at any point in order to reduce the capacitance at critical nodes and consequently increase switching speed. By providing two switching elements with data transistors connected to a common pull-down resistor, two data signals, and a complementary pair of control signals, a multiplexing function can be performed.

Abstract: A switched power amplifier circuit employs non-linear amplifier stages including MOSFET transistors. The transistors each have source, gate, drain and backgate terminals. An input Rf signal is applied to the gate terminals and the source (or drain) terminals are connected to a load. The transistors are operated as switches by selectively applying clock signals to the backgate terminals to activate desired transistors, thus causing the transistors to turn on and allow current to flow through the load to generate power. The power to the load is increased by turning on multiple transistors at any given time.

Abstract: The present invention provides an apparatus and method of tuning the frequency characteristics of a continuous-time filter. First and second test signals are provided to a filter means and the respective first and second responses of the filter means are measured. The first and second responses are compared and based on the comparison a tuning control signal is provided to the filter means to tune the frequency response characteristics of the filter means. During a tuning phase of operation, a first switch connects a test signal generator and disconnects a data signal generator from the transmission input of a continuous-time filter. A signal processor receives a signal from the transmission output from the continuous-time filter and produces a tuning control signal based on that signal. The test signal generator is comprised of means for providing a first test signal, which may be an alternating signal source ("A.C."), and means for providing a second test signal, which may be a direct signal source ("D.C.

Abstract: A preamplifier for use with currents developed by a photodetecting diode is disclosed wherein the currents are coupled to the base of an NPN transistor connected as a common emitter stage and a feedback resistor is connected by way of a buffer amplifier to the base to provide a standard transimpedance configuration. A control loop monitors the signal level by integrating the output of the buffer amplifier, and upon the detection of large signals the control loop causes a MOSFET in parallel with the feedback resistor to decrease the transimpedance and thereby increase the signal handling capability of the preamplifier. The control loop is also connected to a second MOSFET in parallel with the collector load resistor of said NPN transistor to decrease the effective collector load impedance for large signal levels.