Abstract: A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), ?Q+mod(2A,Q), ±1 or ±prime to , where ?<S<+.

Abstract: An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.

Abstract: An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.

Abstract: An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B?1) each addressing more than one and less than all of the memory banks. The interleaves are offset (S) from each adjacent other as to address all of the memory banks equally. An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.

Abstract: A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), ?Q+mod(2A,Q), ±1 or ±prime to , where ?<S<+.

Abstract: A computer processor is responsive to successive processing instructions in an issue order to process regular vectors to generate a result vector without use of a cache. At least two architectural registers having input-vector capability are selectively coupled to memory to receive corresponding vector-elements of two vectors and transfer the vector-elements to a selected functional unit. At least one architectural register having output capability is selectively coupled to an output, which in turn is coupled to transfer result vector-elements to the memory. The functional unit performs a function on the vector-elements to generate a respective result-element. The result-elements are transferred to a selected architectural register for processing as operands in performance of further functions by a functional unit, or are transferred to the output for transfer to memory. In either case, the order of the result vector-elements is restored to the issue order of the successive processing instructions.

Abstract: An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B?1) each addressing more than one and less than all of the memory banks. The interleaves are offset (S) from each adjacent other as to address all of the memory banks equally. An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.

Abstract: A computer processor is responsive to successive processing instructions in an issue order to process regular vectors to generate a result vector without use of a cache. At least two architectural registers having input-vector capability are selectively coupled to memory to receive corresponding vector-elements of two vectors and transfer the vector-elements to a selected functional unit. At least one architectural register having output capability is selectively coupled to an output, which in turn is coupled to transfer result vector-elements to the memory. The functional unit performs a function on the vector-elements to generate a respective result-element. The result-elements are transferred to a selected architectural register for processing as operands in performance of further functions by a functional unit, or are transferred to the output for transfer to memory. In either case, the order of the result vector-elements is restored to the issue order of the successive processing instructions.

Abstract: A register data transmission system has a plurality of register devices connected in series to form a data transmission link between a sending device and a receiving device. This register system can function between independent synchronous operating units of a computer such as a pair of data buffers. As data is transmitted, the individual register devices absorb the data as compactly as necessary within limits, to form the data path. Each register device has two data registers and two control flip-flops. The two data registers are the primary and secondary data rank registers. The secondary data rank register only receives data when the primary data rank register cannot receive data. The two control flip-flops are the primary and secondary full-bit flip-flops. Each register device has a clock control. In operation, data travels from the sending device through each register device to the receiving device while a control signal travels from the receiving device to the sending device.