Abstract: A circuit is provided to produce an output pulse for each analog input pulse whose amplitude and width fall within specified limits. A first amplitude comparator produces a first signal when the amplitude of one of the input pulses exceeds a first reference amplitude and a second amplitude comparator produces a second signal when the width of the one of the input pulses has an amplitude exceeding a second reference amplitude different than the first reference amplitude. Digital circuitry is coupled to the second amplitude comparator to convert the second signal into a binary count, to produce a third signal when the count is greater then a minimum pulse width reference count and to produce a fourth signal when the count is less than a maximum pulse width reference count. A logic gate and pulse generator is coupled to the first amplitude comparator and the digital circuitry responsive to the simultaneous presence of the first, third and fourth signals to produce the circuit output pulse.