Abstract: Received N pseudo random code words and one all logic "0" coded word are stored in a register one code word at a time. An N stage shift register and logic circuitry coupled to each stage of the shift register generate reference N pseudo random code words and one all logic "0" coded word with the bits of all the generated coded words being compared in an EXCLUSIVE OR gate with corresponding bits of a received coded word. The result of the comparison is coupled in common to a largest amplitude value detector which produces a strobe pulse when the amplitude value or the result of the comparison is greater than a preceding largest amplitude value detected and stored. An N stage holding shift register has each stage coupled to the output of the logic circuitry. The strobe pulse clocks the holding register to transfer the generated code word that resulted in the production of the strobe pulse to the holding register.

Abstract: Digital data having a rate R and to be transmitted is converted into a K- code, T-seconds long and delayed according to a particular N-bit word, where N=RT, whereby the code carries information in its delayed position in the T frame and not in the code itself. At a receiver station, the correlation function of the received signal is produced and the envelope detected, after which the samples are taken at each of the K possible output times. The largest output selected comprises the information on the delay of the transmitted signal.