Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing nonnative instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: A process for preparing a divinylarene dioxide including (a) reacting at least one divinylarene with hypochlorous acid to form a chlorohydrin; and (b) treating the chlorohydrin formed in step (a) with at least one base, under conditions to form a divinylarene dioxide product.

Abstract: A structure for coupling together addressably disparate nodes, such as IPv4 nodes and IPv6 nodes, without the use of an application level gateway. Instead, the system includes two executable applications, HEART and ECHO, that avoid the necessity of an application level gateway. In general, HEART and ECHO cooperate with each other through a network address translator-protocol translator (NAT-PT) to cause the NAT-PT to temporarily assign an IPv4 address to a control session between the IPv4 and IPv6 nodes and also prevent the control session from timing out due to lack of timely communications between the IPv4 and IPv6 nodes.

Abstract: A structure for coupling together addressably disparate nodes, such as IPv4 nodes and IPv6 nodes, without the use of an application level gateway. Instead, the system includes two executable applications, HEART and ECHO, that avoid the necessity of an application level gateway. In general, HEART and ECHO cooperate with each other through a network address translator-protocol translator (NAT-PT) to cause the NAT-PT to temporarily assign an IPv4 address to a control session between the IPv4 and IPv6 nodes and also prevent the control session from timing out due to lack of timely communications between the IPv4 and IPv6 nodes.