Abstract: First and second parallel-connected calculating units (12, 18) simultaneously calculate the sum .SIGMA..sub.n =.SIGMA..sub.n-1 +Sn and the difference .SIGMA.'.sub.n =.SIGMA..sub.n-1 -Sn where the Sn is equal to one-half of the difference between the number of 1-bits and the number of 0-bits in a binary word to be transmitted and: ##EQU1## A comparator circuit (22) compares the signs of .SIGMA..sub.n-1 and Sn and the result of the comparison is used to reset the output from one of said calculating units to zero. The sum unit (12, 18) is reset to zero when the signs are different and the difference unit (13, 19) when the signs are equal, in which case the bits of the transmitted word are inverted. The sign comparison bit is also transmitted as an additional bit of the transmitted word.

Abstract: A synchronization device for digital data frame transmission system comprising an n bit series register transferring its contents at the line frequency to a parallel register also of n bits. The m first bits of the series register are also directed to a logic circuit which tests their conformity with the beginning of the synchronization word. When there is conformity, the logic circuit controls a divider dividing by n which controls, in its turn, at the line frequency divided by n, the transfer of the contents of the parallel register to a PROM memory. The purpose of the PROM is to recognize the entire synchronization word. When there is no recognition, the operation of the divide by n divider is inhibited and the procedure begins again.