Patents by Inventor Maurice Rivoire
Maurice Rivoire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865545Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.Type: GrantFiled: March 2, 2017Date of Patent: January 9, 2018Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Maurice Rivoire, Viorel Balan
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Publication number: 20170179035Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Maurice Rivoire, Viorel Balan
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Patent number: 9620412Abstract: A method for modifying crystalline structure of a copper element with a planar surface, including: a) producing a copper standard having large grains, wherein the standard includes a planar surface, b) reducing roughness of the planar surfaces to a roughness of less than 1 nm, c) cleaning the planar surfaces, d) bringing the two planar surfaces into contact, and e) annealing.Type: GrantFiled: July 1, 2010Date of Patent: April 11, 2017Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS (CROLLES 2) SASInventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
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Patent number: 9620385Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.Type: GrantFiled: May 7, 2015Date of Patent: April 11, 2017Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Maurice Rivoire, Viorel Balan
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Publication number: 20150340269Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.Type: ApplicationFiled: May 7, 2015Publication date: November 26, 2015Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Maurice Rivoire, Viorel Balan
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Patent number: 8647983Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.Type: GrantFiled: July 1, 2010Date of Patent: February 11, 2014Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics (Crolles 2) SASInventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
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Patent number: 8562934Abstract: A surface of a substrate comprising microcavities leading out of the substrate is placed in contact with an aqueous solution comprising a plurality of suspended particles and a fabric. Perpendicular pressure is applied the expanse of the substrate between the fabric and the surface of the substrate, and relative movement of the fabric and the surface is applied to the expanse of the substrate. At least one particle is thus fed into each microcavity, therein forming a porous material that is a catalyst material for nanothread or nanotube growth.Type: GrantFiled: March 30, 2009Date of Patent: October 22, 2013Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SASInventors: Jean-Christophe Coiffic, Maurice Rivoire
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Patent number: 8323733Abstract: A surface of a support comprising through micropassages is brought into contact with an aqueous solution comprising a plurality of particles in suspension and a pad. A pressure perpendicular to the plane of the support, between the pad and the surface of the support, and a relative movement of the pad and of the surface in a direction parallel to the plane of the support are applied. At least one particle is thus introduced in each microgap to form a porous material therein.Type: GrantFiled: March 17, 2009Date of Patent: December 4, 2012Assignees: Commisariat a l'Energie Atomique, STMicroelectronics (Crolles 2) SASInventors: Jean-Christophe Coiffic, Maurice Rivoire
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Publication number: 20120100657Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.Type: ApplicationFiled: July 1, 2010Publication date: April 26, 2012Applicants: Stmicroelectronics (Crolles 2) SAS, Commisariat A L'Energie Atomique et Aux Ene AltInventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
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Publication number: 20120097296Abstract: A method for modifying crystalline structure of a copper element with a planar surface, including: a) producing a copper standard having large grains, wherein the standard includes a planar surface, b) reducing roughness of the planar surfaces to a roughness of less than 1 nm, c) cleaning the planar surfaces, d) bringing the two planar surfaces into contact, and e) annealing.Type: ApplicationFiled: July 1, 2010Publication date: April 26, 2012Applicant: COMMISARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALTInventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
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Publication number: 20110034329Abstract: A surface of a substrate comprising microcavities leading out of the substrate is placed in contact with an aqueous solution comprising a plurality of suspended particles and a fabric. Perpendicular pressure is applied the expanse of the substrate between the fabric and the surface of the substrate, and relative movement of the fabric and the surface is applied to the expanse of the substrate. At least one particle is thus fed into each microcavity, therein forming a porous material that is a catalyst material for nanothread or nanotube growth.Type: ApplicationFiled: March 30, 2009Publication date: February 10, 2011Applicants: Commissariat A L'Energie Atomique Et Aux Energies Alternatives, STMicroelectronics (Crolles 2 ) SASInventors: Jean-Christophe Coiffic, Maurice Rivoire
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Patent number: 7713766Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: GrantFiled: November 21, 2008Date of Patent: May 11, 2010Assignee: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire
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Publication number: 20090252871Abstract: A surface of a support comprising through micropassages is brought into contact with an aqueous solution comprising a plurality of particles in suspension and a pad. A pressure perpendicular to the plane of the support, between the pad and the surface of the support, and a relative movement of the pad and of the surface in a direction parallel to the plane of the support are applied. At least one particle is thus introduced in each microgap to form a porous material therein.Type: ApplicationFiled: March 17, 2009Publication date: October 8, 2009Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE, STMICROELECTRONICS (CROLLES 2) SASInventors: Jean-Christophe Coiffic, Maurice Rivoire
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Publication number: 20090075410Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: ApplicationFiled: November 21, 2008Publication date: March 19, 2009Applicant: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire
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Patent number: 7492026Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.Type: GrantFiled: December 30, 2005Date of Patent: February 17, 2009Assignee: STMicroelectronics S.A.Inventors: Danielle Thomas, Maurice Rivoire
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Patent number: 7252695Abstract: Abrasive composition for the integrated circuits electronics industry comprising an aqueous acid suspension of individualized colloidal silica particles not linked to each other by siloxane bonds and an abrasive surfactant, this abrasive being for mechanical chemical polishing in the integrated circuits industry, comprising a fabric impregnated by such a composition, and a process for mechanical chemical polishing.Type: GrantFiled: November 8, 2006Date of Patent: August 7, 2007Assignee: AZ Electronic Materials USA Corp.Inventors: Eric Jacquinot, Pascal Letourneau, Maurice Rivoire
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Patent number: 7200908Abstract: A method of making a variable capacitor by forming a grove portion in an insulating substrate, two upper portions of the substrate located on either side of the groove portion forming two lateral edges, a conductive layer covering the inside of the groove portion, a flexible conductive membrane, placed above the groove portion by bearing on the edges, a dielectric layer covering the conductive layer or the membrane to insulate the conductive layer and the membrane, and terminals of application of a voltage between the conductive layer and the membrane, and such that the depth of the groove portion continuously increases from one of the edges to the bottom of the groove portion, and that the conductive layer covers the inside of the groove portion at least to reach one of the two edges, that it may cover.Type: GrantFiled: May 26, 2006Date of Patent: April 10, 2007Assignees: STMicroelectronics S.A., Commissariat a l'Energie AtomiqueInventors: Fabrice Cassett, Guillaume Bouche, Maurice Rivoire
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Publication number: 20070051918Abstract: Abrasive composition for the integrated circuits electronics industry comprising an aqueous acid suspension of individualized colloidal silica particles not linked to each other by siloxane bonds and an abrasive surfactant, this abrasive being for mechanical chemical polishing in the integrated circuits industry, comprising a fabric impregnated by such a composition, and a process for mechanical chemical polishing.Type: ApplicationFiled: November 8, 2006Publication date: March 8, 2007Applicant: AZ Electronic Materials USA Corp.Inventors: Eric Jacquinot, Pascal Letourneau, Maurice Rivoire
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Patent number: 7144814Abstract: Abrasive composition for the integrated circuits electronics industry comprising an aqueous acid suspension of individualized colloidal silica particles not linked to each other by siloxane bonds and an abrasive surfactant, this abrasive being for mechanical chemical polishing in the integrated circuits industry, comprising a fabric impregnated by such a composition, and a process for mechanical chemical polishing.Type: GrantFiled: October 27, 1999Date of Patent: December 5, 2006Assignee: AZ Electronic Materials USA Corp.Inventors: Eric Jacquinot, Pascal Letourneau, Maurice Rivoire
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Publication number: 20060213044Abstract: A variable capacitor having a groove portion formed in an insulating substrate, two upper portions of the substrate located on either side of the groove portion forming two lateral edges, a conductive layer covering the inside of the groove portion, a flexible conductive membrane, placed above the groove portion by bearing on the edges, a dielectric layer covering the conductive layer or the membrane to insulate the conductive layer and the membrane, and terminals of application of a voltage between the conductive layer and the membrane, and such that the depth of the groove portion continuously increases from one of the edges to the bottom of the groove portion, and that the conductive layer covers the inside of the groove portion at least to reach one of the two edges, that it may cover.Type: ApplicationFiled: May 26, 2006Publication date: September 28, 2006Applicants: STMicroelectronics S.A., Commissariat A L'energie AtomiqueInventors: Fabrice Casset, Guillaume Bouche, Maurice Rivoire