Patents by Inventor Maurice Steinman
Maurice Steinman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200110992Abstract: A system includes a first unit configured to generate a plurality of modulator control signals, and a processor unit. The processor unit includes: a light source or port configured to provide a plurality of light outputs, and a first set of optical modulators coupled to the light source or port and the first unit. The optical modulators in the first set are configured to generate an optical input vector by modulating the plurality of light outputs provided by the light source or port based on digital input values corresponding to a first set of modulator control signals in the plurality of modulator control signals, the optical input vector comprising a plurality of optical signals. The processor unit also includes a matrix multiplication unit that includes a second set of optical modulators.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Inventors: Arash Hosseinzadeh, Yelong Xu, Yanfei Bai, Huaiyu Meng, Ronald Gagnon, Cheng-Kuan Lu, Jonathan Terry, Jingdong Deng, Maurice Steinman, Yichen Shen
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Publication number: 20190370652Abstract: Systems and methods that include: providing input information in an electronic format; converting at least a part of the electronic input information into an optical input vector; optically transforming the optical input vector into an optical output vector based on an optical matrix multiplication; converting the optical output vector into an electronic format; and electronically applying a non-linear transformation to the electronically converted optical output vector to provide output information in an electronic format. In some examples, a set of multiple input values are encoded on respective optical signals carried by optical waveguides. For each of at least two subsets of one or more optical signals, a corresponding set of one or more copying modules splits the subset of one or more optical signals into two or more copies of the optical signals.Type: ApplicationFiled: June 4, 2019Publication date: December 5, 2019Inventors: Yichen Shen, Li Jing, Rumen Dangovski, Peng Xie, Huaiyu Meng, Matthew Khoury, Cheng-Kuan Lu, Ronald Gagnon, Maurice Steinman, Jianhua Wu, Arash Hosseinzadeh
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Patent number: 9360906Abstract: An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed.Type: GrantFiled: May 1, 2013Date of Patent: June 7, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander Branover, Steven Kommrusch, Marvin Denman, Maurice Steinman
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Publication number: 20140331069Abstract: An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed.Type: ApplicationFiled: May 1, 2013Publication date: November 6, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Steven Kommrusch, Marvin Denman, Maurice Steinman
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Patent number: 8484498Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: GrantFiled: August 26, 2010Date of Patent: July 9, 2013Assignee: Advanced Micro DevicesInventors: Alexander Branover, Maurice Steinman, William L. Bircher
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Patent number: 8176352Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.Type: GrantFiled: April 16, 2008Date of Patent: May 8, 2012Assignee: Adavanced Micro Devices, Inc.Inventors: Kevin Gillespie, Guhan Krishnan, Maurice Steinman, Spencer Gold, Bill K. C. Kwan
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Patent number: 8156362Abstract: A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.Type: GrantFiled: August 27, 2008Date of Patent: April 10, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Alexander Branover, Frank Helms, Maurice Steinman
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Publication number: 20120054519Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: ApplicationFiled: August 26, 2010Publication date: March 1, 2012Inventors: Alexander Branover, Maurice Steinman, William L. Bircher
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Patent number: 7941683Abstract: A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.Type: GrantFiled: May 2, 2007Date of Patent: May 10, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Alex Branover, Frank P. Helms, Maurice Steinman
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Patent number: 7870407Abstract: A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.Type: GrantFiled: May 18, 2007Date of Patent: January 11, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Alex Branover, Frank P. Helms, Jonathan M. Owen, Kurt Lewchuk, Maurice Steinman, Paul Mackey
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Patent number: 7856562Abstract: A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.Type: GrantFiled: May 2, 2007Date of Patent: December 21, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice Steinman, Frank Helms, Bill K. C. Kwan, W. Kurt Lewchuk, Paul Mackey
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Publication number: 20090261869Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Kevin GILLESPIE, Guhan KRISHNAN, Maurice STEINMAN, Spencer GOLD, Bill K.C. KWAN
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Publication number: 20090235105Abstract: A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.Type: ApplicationFiled: August 27, 2008Publication date: September 17, 2009Inventors: Alexander Branover, Frank Helms, Maurice Steinman
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Publication number: 20080288799Abstract: A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.Type: ApplicationFiled: May 18, 2007Publication date: November 20, 2008Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Alex Branover, Frank P. Helms, Jonathan M. Owen, Kurt Lewchuk, Maurice Steinman, Paul Mackey
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Publication number: 20080276236Abstract: A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Alex Branover, Frank P. Helms, Maurice Steinman
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Publication number: 20080276026Abstract: A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Alexander Branover, Maurice Steinman, Frank Helms, Bill K.C. Kwan, W. Kurt Lewchuk, Paul Mackey
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Publication number: 20070115290Abstract: In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.Type: ApplicationFiled: November 23, 2005Publication date: May 24, 2007Inventors: R. Polzin, Richard Witek, Maurice Steinman
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Publication number: 20070067514Abstract: In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Warren Anderson, Maurice Steinman, Richard Watson, Horst Wagner, Christopher Gianos, Suresh Balasubramanian, Tim Frodsham
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Publication number: 20050281203Abstract: Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.Type: ApplicationFiled: June 22, 2004Publication date: December 22, 2005Inventors: Naveen Cherukuri, Tim Frodsham, Eduard Roytman, Sanjay Dabral, Rahul Shah, Theodore Schoenborn, Maurice Steinman, David Dunning
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Publication number: 20050262284Abstract: A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.Type: ApplicationFiled: May 21, 2004Publication date: November 24, 2005Inventors: Naveen Cherukuri, Sanjay Dabral, David Dunning, Tim Frodsham, Theodore Schoenborn, Rahul Shah, Maurice Steinman