Patents by Inventor Maurice Wilhelmus Leonardus Hendricus Feijts

Maurice Wilhelmus Leonardus Hendricus Feijts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Contamination trap
    Patent number: 11982947
    Abstract: A contamination trap for use in a debris mitigation system of a radiation source, the contamination trap comprising a plurality of vanes configured to trap fuel debris emitted from a plasma formation region of the radiation source; wherein at least one vane or each vane of the plurality of vanes comprises a material comprising a thermal conductivity above 30 W m?1 K?1.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 14, 2024
    Assignee: ASML NETHERLAND B.V.
    Inventors: Sander Catharina Reinier Derks, Daniel Jozef Maria Direcks, Maurice Wilhelmus Leonardus Hendricus Feijts, Pieter Gerardus Mathijs Hoeijmakers, Katja Cornelia Joanna Clasina Moors, Violeta Navarro Paredes, William Peter Van Drent, Jan Steven Christiaan Westerlaken
  • CONTAMINATION TRAP
    Publication number: 20230091648
    Abstract: A contamination trap for use in a debris mitigation system of a radiation source, the contamination trap comprising a plurality of vanes configured to trap fuel debris emitted from a plasma formation region of the radiation source; wherein at least one vane or each vane of the plurality of vanes comprises a material comprising a thermal conductivity above 30 W m?1 K?1.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Applicant: ASML Netherlands B.V.
    Inventors: Sander Catharina Reinier DERKS, Daniel Jozef Maria DIRECKS, Maurice Wilhelmus Leonardus Hendricus FEIJTS, Pieter Gerardus Mathijs HOEIJMAKERS, Katja Cornelia Joanna Clasina MOORS, Violeta NAVARRO PAREDES, William Peter VAN DRENT, Jan Steven Christiaan WESTERLAKEN
  • Contamination trap
    Patent number: 11556067
    Abstract: A contamination trap for use in a debris mitigation system of a radiation source, the contamination trap comprising a plurality of vanes configured to trap fuel debris emitted from a plasma formation region of the radiation source; wherein at least one vane or each vane of the plurality of vanes comprises a material comprising a thermal conductivity above 30 W m?1K?1.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: January 17, 2023
    Assignee: ASML Netherlands B.V.
    Inventors: Sander Catharina Reinier Derks, Daniel Jozef Maria Direcks, Maurice Wilhelmus Leonardus Hendricus Feijts, Pieter Gerardus Mathijs Hoeijmakers, Katja Cornelia Joanna Clasina Moors, Violeta Navarro Paredes, William Peter Van Drent, Jan Steven Christiaan Westerlaken
  • Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder
    Patent number: 10018924
    Abstract: A substrate holder for a lithographic apparatus has a planarization layer provided on a surface thereof. The planarization layer provides a smooth surface for the formation of a thin film stack forming an electronic component. The thin film stack comprises an (optional) isolation layer, a metal layer forming an electrode, a sensor, a heater, a transistor or a logic device, and a top isolation layer.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 10, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Raymond Wilhelmus Louis Lafarre, Nicolaas Ten Kate, Nina Vladimirovna Dziomkina, Yogesh Pramod Karade, Siegfried Alexander Tromp, Jacobus Josephus Leijssen, Elisabeth Corinne Rodenburg, Maurice Wilhelmus Leonardus Hendricus Feijts, Hendrik Huisman
  • SUBSTRATE HOLDER, LITHOGRAPHIC APPARATUS, DEVICE MANUFACTURING METHOD, AND METHOD OF MANUFACTURING A SUBSTRATE HOLDER
    Publication number: 20160170314
    Abstract: A substrate holder for a lithographic apparatus has a planarization layer provided on a surface thereof. The planarization layer provides a smooth surface for the formation of a thin film stack forming an electronic component. The thin film stack comprises an (optional) isolation layer, a metal layer forming an electrode, a sensor, a heater, a transistor or a logic device, and a top isolation layer.
    Type: Application
    Filed: February 3, 2016
    Publication date: June 16, 2016
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Raymond Wilhelmus Louis LAFARRE, Nicolaas TEN KATE, Nina Vladimirovna DZIOMKINA, Yogesh Pramod KARADE, Siegfried Alexander TROMP, Jacobus Josephus LEIJSSEN, Elisabeth Corinne RODENBURG, Maurice Wilhelmus Leonardus Hendricus FEIJTS, Hendrik HUISMAN
  • Substrate holder, lithographic apparatus, device manufacturing method, and method of manufacturing a substrate holder
    Patent number: 9256139
    Abstract: A substrate holder for a lithographic apparatus has a planarization layer provided on a surface thereof. The planarization layer provides a smooth surface for the formation of a thin film stack forming an electronic component. The thin film stack comprises an (optional) isolation layer, a metal layer forming an electrode, a sensor, a heater, a transistor or a logic device, and a top isolation layer.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 9, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Raymond Wilhelmus Louis Lafarre, Nicolaas Ten Kate, Nina Vladimirovna Dziomkina, Yogesh Pramod Karade, Siegfried Alexander Tromp, Jacobus Josephus Leijssen, Elisabeth Corinne Rodenburg, Maurice Wilhelmus Leonardus Hendricus Feijts, Hendrik Huisman