Patents by Inventor Mauricio Breternitz

Mauricio Breternitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10866768
    Abstract: A cluster compute server stores different types of data at different storage volumes in order to reduce data duplication at the storage volumes. The storage volumes are categorized into two classes: common storage volumes and dedicated storage volumes, wherein the common storage volumes store data to be accessed and used by multiple compute nodes (or multiple virtual servers) of the cluster compute server. The dedicated storage volumes, in contrast, store data to be accessed only by a corresponding compute node (or virtual server).
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 15, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Jr., Leonardo Piga
  • Patent number: 10558466
    Abstract: Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means clustering algorithm, the processor determines that a first plurality of data points belong to a first group during a given iteration. If the first plurality of data points is not an integer multiple of the number of processing lanes, then the processor reassigns a first number of data points from the first plurality of data points to one or more other groups. The processor then performs the next iteration with these first number of data points assigned to other groups even though the first number of data points actually meets the algorithmic criteria for belonging to the first group.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: February 11, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Mayank Daga
  • Patent number: 10318153
    Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g., computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 11, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Mitesh Ramesh Meswani, Gabriel H. Loh, Mauricio Breternitz, Jr., Mark Richard Nutter, John Robert Slice, David Andrew Roberts, Michael Ignatowski, Mark Henry Oskin
  • Patent number: 10318340
    Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: June 11, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Gabriel H. Loh, Mauricio Breternitz
  • Patent number: 10271008
    Abstract: Systems, apparatuses, and methods for enhanced resolution video and security via machine learning are disclosed. A transmitter reduces a resolution of each image of a videostream from a first, higher image resolution to a second, lower image resolution. The transmitter generates a set of parameters for programming a neural network to reconstruct a version of each image at the first image resolution. Then, the transmitter sends the images at the second image resolution to the receiver, along with the first set of parameters. The receiver programs a neural network with the first set of parameters and uses the neural network to reconstruct versions of the images at the first image resolution. The transmitter can send the first set of parameters to the receiver via a secure channel, ensuring that only the receiver can decode the images from the second image resolution to the first image resolution.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, John E. Owen, Jr.
  • Patent number: 10198349
    Abstract: Systems, apparatuses, and methods for utilizing in-memory accelerators to perform data conversion operations are disclosed. A system includes one or more main processors coupled to one or more memory modules. Each memory module includes one or more memory devices coupled to a processing in memory (PIM) device. The main processors are configured to generate an executable for a PIM device to accelerate data conversion tasks of data stored in the local memory devices. In one embodiment, the system detects a read request for data stored in a given memory module. In order to process the read request, the system determines that a conversion from a first format to a second format is required. In response to detecting the read request, the given memory module's PIM device performs the conversion of the data from the first format to the second format and then provides the data to a consumer application.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Walter B. Benton
  • Publication number: 20180314945
    Abstract: Systems, apparatuses, and methods for enhanced resolution video and security via machine learning are disclosed. A system is configured to receive a source code representation of a neural network. In one embodiment, the source code representation is a directed acyclic graph (DAG). The system determines if the source code representation includes any of one or more patterns, with each pattern including two or more adjacent layers. The system also identifies, for each pattern, a combined layer with which to replace the detected pattern. If any occurrences of the one or more patterns are detected in the source code representation, the system replaces each pattern with a corresponding combined layer. Additionally, the system generates an optimized representation of the neural network, wherein the optimized representation includes replacements for any detected patterns. The optimized representation can be utilized to generate an executable version of the neural network.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 1, 2018
    Inventors: Mauricio Breternitz, Mayank Daga
  • Publication number: 20180295320
    Abstract: Systems, apparatuses, and methods for enhanced resolution video and security via machine learning are disclosed. A transmitter reduces a resolution of each image of a videostream from a first, higher image resolution to a second, lower image resolution. The transmitter generates a set of parameters for programming a neural network to reconstruct a version of each image at the first image resolution. Then, the transmitter sends the images at the second image resolution to the receiver, along with the first set of parameters. The receiver programs a neural network with the first set of parameters and uses the neural network to reconstruct versions of the images at the first image resolution. The transmitter can send the first set of parameters to the receiver via a secure channel, ensuring that only the receiver can decode the images from the second image resolution to the first image resolution.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 11, 2018
    Inventors: Mauricio Breternitz, John E. Owen, JR.
  • Patent number: 10089155
    Abstract: First and second processor cores are configured to concurrently execute tasks. A scheduler is configured to schedule tasks for execution by the first and second processor cores. The first processor core is configured to selectively steal a task that was previously scheduled for execution by the second processor core based on additional power consumption incurred by migrating the task from the second processor core to the first processor core.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 2, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Deepak Majeti, Mauricio Breternitz
  • Patent number: 10067709
    Abstract: Systems, apparatuses, and methods for accelerating page migration using a two-level bloom filter are disclosed. In one embodiment, a system includes a GPU and a CPU and a multi-level memory hierarchy. When a memory request misses in a first memory, the GPU is configured to check a first level of a two-level bloom filter to determine if a page targeted by the memory request is located in a second memory. If the first level of the two-level bloom filter indicates that the page is not in the second memory, then the GPU generates a page fault and sends the memory request to a third memory. If the first level of the two-level bloom filter indicates that the page is in the second memory, then the GPU sends the memory request to the CPU.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Leonardo Piga, Mauricio Breternitz
  • Patent number: 10019365
    Abstract: Enhanced adaptive profiling of ranges of values in a stream of events includes identifying a set of contiguous ranges of the values and corresponding access frequencies in the stream of events. The enhanced adaptive profiling uses a merge threshold value and a split threshold value. The set of contiguous ranges spans an entire range space of the values. Periodic traversal of the set of contiguous ranges of values and corresponding access frequencies identifies a target set of ranges of the values having corresponding access frequencies above a predetermined threshold access frequency. The target set of ranges of values has a total number of ranges less than or equal to a predetermined number of ranges. The target ranges of values span at least some of the entire range space of values. A first operation uses the target set of ranges of values.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 10, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mauricio Breternitz
  • Publication number: 20180081585
    Abstract: Systems, apparatuses, and methods for accelerating page migration using a two-level bloom filter are disclosed. In one embodiment, a system includes a GPU and a CPU and a multi-level memory hierarchy. When a memory request misses in a first memory, the GPU is configured to check a first level of a two-level bloom filter to determine if a page targeted by the memory request is located in a second memory. If the first level of the two-level bloom filter indicates that the page is not in the second memory, then the GPU generates a page fault and sends the memory request to a third memory. If the first level of the two-level bloom filter indicates that the page is in the second memory, then the GPU sends the memory request to the CPU.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Leonardo Piga, Mauricio Breternitz
  • Publication number: 20180081583
    Abstract: Systems, apparatuses, and methods for utilizing in-memory accelerators to perform data conversion operations are disclosed. A system includes one or more main processors coupled to one or more memory modules. Each memory module includes one or more memory devices coupled to a processing in memory (PIM) device. The main processors are configured to generate an executable for a PIM device to accelerate data conversion tasks of data stored in the local memory devices. In one embodiment, the system detects a read request for data stored in a given memory module. In order to process the read request, the system determines that a conversion from a first format to a second format is required. In response to detecting the read request, the given memory module's PIM device performs the conversion of the data from the first format to the second format and then provides the data to a consumer application.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Mauricio Breternitz, Walter B. Benton
  • Publication number: 20170371665
    Abstract: Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means clustering algorithm, the processor determines that a first plurality of data points belong to a first group during a given iteration. If the first plurality of data points is not an integer multiple of the number of processing lanes, then the processor reassigns a first number of data points from the first plurality of data points to one or more other groups. The processor then performs the next iteration with these first number of data points assigned to other groups even though the first number of data points actually meets the algorithmic criteria for belonging to the first group.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Mauricio Breternitz, Mayank Daga
  • Patent number: 9817644
    Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Mauricio Breternitz, Jr., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
  • Patent number: 9766936
    Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 19, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh, Yasuko Eckert
  • Publication number: 20170212837
    Abstract: Enhanced adaptive profiling of ranges of values in a stream of events includes identifying a set of contiguous ranges of the values and corresponding access frequencies in the stream of events. The enhanced adaptive profiling uses a merge threshold value and a split threshold value. The set of contiguous ranges spans an entire range space of the values. Periodic traversal of the set of contiguous ranges of values and corresponding access frequencies identifies a target set of ranges of the values having corresponding access frequencies above a predetermined threshold access frequency. The target set of ranges of values has a total number of ranges less than or equal to a predetermined number of ranges. The target ranges of values span at least some of the entire range space of values. A first operation uses the target set of ranges of values.
    Type: Application
    Filed: April 15, 2016
    Publication date: July 27, 2017
    Inventor: Mauricio Breternitz
  • Patent number: 9658895
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes with the selected boot-time configuration to modify at least one boot-time parameter of the at least one node.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 23, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Patent number: 9639140
    Abstract: A method of managing power state transitions for an interactive workload includes storing one or more parameters, each representing an electrical operating characteristic that controls power consumption of the processing unit, receiving a first user input requesting execution of a task by the processing unit, in response to receiving a second user input, modifying at least one of the one or more parameters, and executing the task in the processing unit while operating the processing unit according to the at least one modified parameter.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 2, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Leonardo de Paula Rosa Piga, Mauricio Breternitz
  • Publication number: 20170083074
    Abstract: A method of managing power state transitions for an interactive workload includes storing one or more parameters, each representing an electrical operating characteristic that controls power consumption of the processing unit, receiving a first user input requesting execution of a task by the processing unit, in response to receiving a second user input, modifying at least one of the one or more parameters, and executing the task in the processing unit while operating the processing unit according to the at least one modified parameter.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Leonardo de Paula Rosa Piga, Mauricio Breternitz