Abstract: A method, machine readable medium, and system are disclosed. In one embodiment the method comprises collecting a loop trip count continuously during runtime of a region of code being executed that contains a loop, categorizing the trip count to identify one or more code modification techniques applicable to the loop, and dynamically applying the one or more applicable code modification techniques to alter the code that relates to the loop.

Abstract: Method of monitoring a secure encrypted communication, where the encryption key(s) is recovered by an escrow center having a master and multiple agents and the master receives the key encrypted using a mask scheme. Independent random masks are generated, which are then used to create dependent masks for each agent. The agents receive the mask information but no key information. The agents decide whether to allow the interception of an encrypted message. In response to the agents' decisions, the master is either enabled to recover the key or prevented from recovering the key. Encrypted key information is only available to the master. Multiple combinations of agents will provide sufficient information to the master to recover the key, avoiding the hold-out problems of the prior art. In one embodiment, multiple masters provide back-up protection when a master is unavailable.

Abstract: A cache line of a cache (230) contains a modifiable instruction. The modifiable instruction is decoded by a central processor unit (210) (CPU) which performs the function associated with the modifiable instruction. After the modifiable instruction has been executed, the CPU (210) sets an instruction modified bit associated with the cache (200) based on the execution results of the modifiable instruction. During a subsequent process of the modifiable instruction location, the CPU Decode Unit (212) substitutes a modified instruction for the modifiable instruction based on the instruction modify indicator.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: A compiler (142) constructs (FIGS. 14-32) a Reduced Flowgraph (RFG) from computer source code (144). The RFG is used to instrument (FIG. 36) code (142). An object module is created (146) and executed (148). Resulting path frequency counts are written to a counts file (154). A compiler (158) uses the source code (144) and the generated counts to identify runtime correlations between successive path edges and Superedges. An object module (159) is generated containing reordered (156) code generated to optimize performance based on the runtime correlations. If cloning is enabled (152), high frequency path edges are cloned (154) or duplicated to minimize cross edge branching.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: An instruction set interpreter and translator provides dynamic idiom recognition by use of a programmable hash table. Idioms are sequences of consecutive instructions that occur frequently during execution. Interpretive execution of such idioms is optimized to attain high performance. Idioms are recognized dynamically during interpretive execution. A programmable hash table is extended with entries corresponding to newly recognized idioms as their frequency of occurrence exceeds a threshold.

Abstract: Data is allocated into multiple memories with selective variable replication for maximizing performance by minimizing concurrent memory access conflicts. Requirements for concurrent access are summarized in a transformed concurrent access graph. Graph vertices are merged to disallow variable replication. All potential graph merges that cause a reduction in machine cycle time are identified. The ratios of saved cycles/memory cost in bytes are then computed for each potential merge. The potential merges are then sorted by their saved cycles/bytes ratio. Finally, potential merges resulting in replicated variables are selected based on their cycles/bytes ratios until a predefined memory target size is achieved. Either graph coloring or clique partitioning can be used to allocate variables into memory banks.

Abstract: A method and apparatus for sequencing computer instructions in memory (24) to provide for more instruction efficient execution by a central processing unit (CPU) (22) begins by executing the computer instructions via the CPU (22) and creating a trace file (FIG. 2) in memory (24). The trace file is then scanned using a window size greater than two (i.e., more than two instructions or basic blocks/ groups of instructions are selected as each window) and correlations are determined between several pairs of instructions in each window (FIGS. 9 and 10). The correlations obtained by the window procedure are then analyzed (FIG. 11) to determine an efficient ordering of computer instructions for subsequent execution by any target CPU.

Abstract: A native microprocessor (20) accesses a foreign block of computer code. An initial block scope defining translation parameters is assigned to the block (106). The block of "foreign" code is translated to "native" code (108). An optimization efficiency is calculated for the translated block (110). A rescheduling criterion is established based on the optimization efficiency (112). The block of native code is executed (114). On subsequent accesses of the block when the reschedule criterion is met (116) the block scope is redefined (118).

Abstract: In a data processing system, a plurality of prefetch elements are provided for prefetching instructions from a group of memory arrays coupled to each prefetch element. A plurality of instruction words are sequentially stored in each group of memory arrays coupled to each prefetch element. In response to a selected prefetch element receiving a prefetch token, the selected prefetch element sequentially recalls instruction words from the group of memory arrays coupled to the selected prefetch element. Thereafter, the selected prefetch element transfers the sequence of instruction words to a central processing unit at a rate of one instruction word per cycle time. In response to a forthcoming conditional branch instruction, a plurality of prefetch elements may initiate instruction fetching so that the proper instruction may be executed during the cycle time immediately following the conditional branch instruction.

Abstract: In a data processing system, a tag memory is divided into a first tag memory portion and a second tag memory portion. Next, an address for recalling requested data is generated by a central processing unit. Thereafter, a first and second tag memory addresses are concurrently computed, where the first and second tag memory addresses have bits which differ in value in a selected corresponding bit location. In response to the value of the bit in the selected bit location, the first tag memory address is coupled to either the first or second tag memory portion, and, concurrently, the second tag memory address is coupled to the other tag memory portion. Next, tag data is concurrently recalled from both the first and second tag memory portions utilizing the first and second tag memory addresses. A search tag is generated in response to the memory address from the CPU. Thereafter, the search tag and the recalled tag data from the first and second tag memory portions are concurrently compared.

Abstract: In a data processing system, a plurality of primary and secondary prefetch elements are provided for prefetching a primary portion and a secondary portion of instruction words from a group of primary and secondary memory arrays coupled to each primary and secondary prefetch element, respectively. In response to a selected primary or secondary prefetch element receiving a prefetch token, the selected primary or secondary prefetch element sequentially recalls instruction words from the group of primary or secondary memory arrays, respectively. In response to a forthcoming conditional branch instruction, a plurality of prefetch elements may initiate instruction fetching so that the proper instruction may be executed during the cycle time immediately following the conditional branch instruction.

Abstract: A method for eliminating redundant loads in an optimizing compiler is provided. When a LOAD and memory operation occur in an iterative loop structure having an induction variable, the method determines if redundant load elimination optimization may be performed by performing the steps of: creating a symbolic address for a LOAD operation, where the LOAD operation follows a memory operation, creating a symbolic address for the memory operation which precedes the LOAD, and subtracting the LOAD symbolic address from the memory operation symbolic address to generate a difference. If the difference is a constant which is divisible by the increment of the induction variable, the method eliminates the LOAD instruction for each increment of the loop and includes an instruction to copy the value of the memory operation to a register, and further includes an instruction to move the copied value from the register to the target of the load.