Abstract: A method of generating timing signals for constant bit rate data received over an asynchronous data network carrying, comprises recovering clock signals from at least two separate sources, selecting one of the sources to drive a phase-locked loop generating a high speed output signal locked to the selected source, dividing the high speed output signal to provide the required timing signals for said constant bit rate data, and continually monitoring the selected source. In the event of failure of the selected source, the phase-locked loop is allowed to free run in a hold-over mode while it is switched over to the other source.

Abstract: A method of controlling the supply of cells into an asynchronous network, comprises the steps of storing incoming bytes from multiple channels in respective channel buffers, creating in memory a timing event wheel partitioned into a plurality of sectors, of which one is active at any time, and placing cell pointers in the sectors. The cell pointers identify channel buffers and are distributed around the wheel in accordance with a desired transmission schedule. The wheel is stepwise advanced at a predetermined rate, and the cell pointers in the active sector are scanned at each advance of the wheel to identify the corresponding channel buffers. The bytes from the identified channel buffers are assembled into cells, which are forwarded for transmission over the asynchronous network. These are then multiplexed with VBR cells from another source.

Abstract: A telecommunications system comprises a plurality of servers interconnected by a TDM backbone and able to share a common channel or bandwidth. An arrangement for sending messages or files between said servers comprises a master node for sending a continuous stream of cells round the backbone, each cell having a header portion and a payload portion, and a plurality of downstream nodes which upon arrival of incoming cells insert information therein, read information therefrom, or allow the cells to pass thereby unaltered.

Abstract: A digital switch array, includes a serial input bus providing a plurality of input streams, each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams, each defining a plurality of time division multiplexed output channels, and an array of digital switches arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device for each output timeslot so that when the enabling device is enabled the associated output timeslot is driven, and at least first and second enabling inputs which when simultaneously activated cause the enabling device to become enabled. An array of activation lines are arranged in rows and columns.

Abstract: An interface device serving as a bridge between a telephone-based bus with a plurality of TDM channels and a high speed data network to permit mixed data, voice, and video signals to be exchanged between the telephone bus and the data network, comprises a serial port for connection to the telephone bus; a parallel port for connection to the high speed data network; a bidirectional serial-to-parallel/parallel-to-serial converter connected to the serial port; and a rate converter circuit between the bidirectional converter and said parallel port, the rate converter circuit including a time-slot interchange device to permit rate adaptation with constant throughput delay and switching between the TDM channels.