Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.

Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.

Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.

Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.

Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.

Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.

Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with the architecture of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate of deactivate a memory block in response to a system call from the power savings manager.

Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.

Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.

Abstract: A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.

Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.

Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.

Abstract: A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.

Abstract: An integrated circuit chip which has a volatile memory also has a non-volatile memory for storing the parameter of a volatile memory which was measured while the chip was part of a completed wafer.

Abstract: A memory module, such as a Single In Line Memory Module (SIMM), is provided which utilizes defective, substandard and/or unconventional memory devices to provide functionality that is equivalent to a memory module constructed with fully operational standard memory devices.

Abstract: A solid state disc (SSD) Memory comprising the following functional blocks: a memory block (DATA ARRAY) wherein check data bytes are written; a transcoder memory block (SCRAMBLE RAM) which contains the table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (SCRAM DEC) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code (ECC) block for implementing the error correction algorithm; an input buffer block (LOGICAL ROW ADDRESS BUFFER) for storing the row addresses coming from the external bus; a non-volatile memory block, programmed during the test stage and available to a possible processor for handling the contents of the transcoder memory (SCRAMBLE RAM); a word counter block (WORD COUNTER) that is driven from the external clock signal (clock) and counts the number of the addressed words and generates the

Abstract: System for enabling the use of semiconductor dynamic memories having faulty locations therein where the memory is organized in banks for forming an elementary information word. The system identifies all homologous address locations which are not faulty, and the non-faulty locations are then stored as a map in a non-volatile read-only-memory related to the memory bank so as to form a transcoding table. Access to the memory blocks involves the use of a central processing unit requesting access to a block identified by a sequential address. The system then provides for associating the material address of a block of the memory array to the logical address, this association or transcoding operation being carried out by the non-volatile read-only-memory.