Abstract: A driver circuit includes a half-bridge output stage including two transistors with a common terminal for connection as the driver output to a coil of a DC motor. Two amplifiers drive the transistors in the push-pull operation and two capacitors are connected between the driver output and one input of a respective amplifier to form feedback loops for controlling the output slew-rate. Two current generators are selectively connected to an input of either of the amplifiers through respective pairs of switches. A commutation sequencer turns on and off the switches according to a commutation program. Comparators are connected to the drive output for detecting predetermined output voltage conditions and providing the commutation sequencer with signals for conditioning the commutation program as a function of the detected voltage conditions.

Abstract: A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.

Abstract: The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.

Abstract: A BEMF detector and method detect the BEMF of a three-phase motor using a fully differential detection system. The motor has a first coil coupled between a first coil tap and a center tap, a second coil coupled between a second coil tap and the center tap, and a third coil coupled between a third coil tap and the center tap. The BEMF detector includes a differential amplifier having first and second inputs and first and second outputs, with the first input being coupled to one of the coil taps and the second input being coupled to the center tap. The BEMF detector also includes a comparator having first and second inputs coupled respectively to the first and second outputs of the differential amplifier and an output at which a BEMF signal is produced that is related to the BEMF of the motor. The differential amplifier may be part of an anti-alias filter structured to fix to a known stable value a common mode at the outputs of the differential amplifier.

Abstract: A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

Abstract: A digital-to-analog converter includes a potentiometric string suitable for realizing a relatively high number of bits that significantly reduces the silicon area requirement and simplifies mismatch compensation. The structure includes a first resistance string to realize a first DAC to convert a first number of most significative bits, and a second potentiometric string functionally connected in cascade to the first, but realized with MOS transistors. The structure of the invention allows the coupling of the two DACs in cascade by exploiting the MOS transistors that form the second potentiometric string, that is, the second DAC, thus avoiding the use of operational switches or amplifiers which may provide error sources. Moreover, the structure of the invention lends itself to the implementation of efficient compensation circuits for integral and differential linearity errors.

Abstract: Masking of switching noise is implemented in the driving system of an "H" bridge stage by exploiting the periodic signal generated by a PWM control circuit (normally present in the control system for controlling the "H" bridge in an open-loop mode) for masking the decay time of the disturbances caused by the switching from off-to-on of a first pair of switches of the bridge that drive a current in a certain direction through the load. This is implemented by keeping high for a preset period of time the periodic signal generated by the PWM circuit and varying the duty-cycle of the signal for regulating the mask time in function of the load characteristics.

Abstract: A fast-discharge switch is controlled by a comparator sensing the voltage difference between the output node and the input node of a driving integrator stage that controls the slew-rate of a power switching output transistor. The fast-discharge switch turns off automatically when the output power transistor reaches (in the case of a MOS transistor) or exits (in the case of a bipolar transistor) saturation. The circuit of the invention accelerates the discharge thus reducing the turn-off delay and is insensitive of load conditions and does not affect the performance of the integrating (driver) stage that control the slew-rate.

Abstract: In a half-bridge output stage employing a complementary pair of output power transistors, each driven through an integrating stage for controlling the slew-rate, a single integration capacitance is conveniently shared by the two integrating stages that drive the power transistors. A pair of switches connect the single integrating capacitance to the input of either one of the two integrating stages and are controlled by a pair of nonoverlapping signals that have a certain advance with respect to the pair of logic signals that drive the half-bridge stage. In the case of a driving system of a multi-phase machine, the two configuring switches of the single integration capacitor may be driven by a pair of control signals that drive a different phase winding of the multi-phase machine, thus eliminating the need for dedicated circuitry for generating said pair of anticipated signals to control the configuration switches.

Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.