Abstract: A decoder for audio signals belonging to audio-visual streams coded in accordance with standard ISO/IEC 11172 is provided. The decoder has a presentation unit (UP) which is controlled by a first and a second clock signal, depending on the desired sampling rate, and is associated to device for (SAV) managing audio-video synchronization. The latter device starts the presentation of output data by comparing a first timing signal (SCR), representative of a system clock signal, and a second timing signal (PTS), representative of a correct instant of data presentation, independently generate the two clock signals (CLK24, CLK22) and corrects the signal corresponding to the desired sampling rate with the use of a feedback circuit which includes a digital filter (FD).

Abstract: This connected-speech recognition system uses a two-level hierarchical system, in which the higher-level (master) processor and one or more lower-level units (slaves) process, respectively, the most probably word sequence within a permitted grammar network, and the likelihood of individual words with the grammar network. The lower-level processing performs dynamic programming involving vector and matrix calculation and comparison, and processing speed is improved by an integrated processing unit which has simultaneous access to the external data memory as well as to a high-speed internal microinstruction ROM. One of the aforementioned units can also provide for performing an additional internal test function. The structure features two internal data buses and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access.

Abstract: The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional fields (CS, FS) carrying the encoding, in Modified Berger code, of the allocation address of the microinstruction itself and of the following one. The microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM). The two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences represent unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).