Abstract: A transceiver circuit with a front-end and a back-end is provided. The front-end has terminals for coupling to a first and a second capacitor and tunable resistors coupled between the terminals and a reference terminal. The front-end is configured to receive receiver signals at the terminals utilizing a first setting for the resistors. The front-end is configured to generate a receiver data packet based on the receiver signals. The back-end is configured to check the receiver data packet for errors with respect to a defined tuning data packet. If an error is found, the back-end sets the resistors to a default setting. If no errors are found, the back-end sets the resistors to a second setting.

Abstract: A connector for capacitive coupling of a first communicator and a second communicator of a communication system has a first, a second, a third and a fourth electrode, all of which are electrically conductive. The first and third electrodes are designed to be coupled to the first communicator. The second and fourth electrodes are designed to be coupled to the second communicator. The electrodes are designed to constitute capacitive couplings. Additionally, the first and the second electrode are designed to induce an attractive force between themselves by using a magnetic interaction. Analogously, the third and the fourth electrode are designed to induce an attractive force between themselves by using a magnetic interaction.

Abstract: A transceiver circuit with a front-end and a back-end is provided. The front-end has terminals for coupling to a first and a second capacitor and tunable resistors coupled between the terminals and a reference terminal. The front-end is configured to receive receiver signals at the terminals utilizing a first setting for the resistors. The front-end is configured to generate a receiver data packet based on the receiver signals. The back-end is configured to check the receiver data packet for errors with respect to a defined tuning data packet. If an error is found, the back-end sets the resistors to a default setting. If no errors are found, the back-end sets the resistors to a second setting.

Abstract: A method for channel switching comprising the steps: establishing (10) an active communication in a channel ch(m), checking (11) if the communication at an actual timeslot t(n) is successful, if checking (11) if the communication at the actual timeslot t(n) is successful, keeping the communication using the channel ch(m) for a next timeslot t(n+1) and repeating checking (11) if the communication at the actual timeslot t(n) is successful, if checking (11) if the communication at the actual timeslot t(n) is not successful, initiating a selection of a next channel ch(m+1). Further a device for communication is presented.

Abstract: A method for channel switching comprising the steps: establishing (10) an active communication in a channel ch(m), checking (11) if the communication at an actual timeslot t(n) is successful, if checking (11) if the communication at the actual timeslot t(n) is successful, keeping the communication using the channel ch(m) for a next timeslot t(n+1) and repeating checking (11) if the communication at the actual timeslot t(n) is successful, if checking (11) if the communication at the actual timeslot t(n) is not successful, initiating a selection of a next channel ch(m+1). Further a device for communication is presented.

Abstract: An amplifier arrangement having a transistor arrangement comprising a first transistor (1) in common-emitter configuration and a second transistor (2) in common-base configuration. A switching device (7) couples, in a first mode of operation, the first transistor (1) to an input (3) of the amplifier arrangement and while the second transistor (2) forms a cascade stage. In a second mode of operation the second transistor (2) is coupled to the input (3). While high gain is achieved during the first mode, the second mode allows for high linearity without requiring inductive degeneration.

Abstract: An amplifier arrangement having a transistor arrangement comprising a first transistor (1) in common-emitter configuration and a second transistor (2) in common-base configuration. A switching device (7) couples, in a first mode of operation, the first transistor (1) to an input (3) of the amplifier arrangement and while the second transistor (2) forms a cascade stage. In a second mode of operation the second transistor (2) is coupled to the input (3). While high gain is achieved during the first mode, the second mode allows for high linearity without requiring inductive degeneration.