Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract: A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract: A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.

Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

Abstract: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.

Abstract: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.

Abstract: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

Abstract: A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.

Abstract: A memory device having an associative memory for the storage of data belonging to a plurality of classes. The associative memory has a plurality of memory locations aligned along rows and columns for the storage of data along the rows. Each memory row has a plurality of groups of memory locations, each storing a respective datum, wherein groups of memory locations adjacent along one and the same row store data belonging to different classes. Groups of memory locations adjacent in the direction of the columns and disposed on different rows store data belonging to one and the same class. Each class has data having a different maximum lengths. The device is particularly suitable for the storage of words belonging to a dictionary for automatic recognition of words in a written text.

Abstract: A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.

Abstract: A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.