Abstract: A test circuit includes a set of electronic switches having a current path between a first node and a ground node, where each electronic switch has a respective control node. A set of coupling channels have one end coupled to a common test node and other ends coupled to the respective control nodes of electronic switches. A stress voltage supply source is coupled to the common test node. A set of comparator circuits includes comparator circuits having a first input node coupled, via sensing circuitry, to the control node of respective electronic switches in the set of electronic switches and having second nodes coupled to a threshold voltage node. A method of operating the test circuit is also disclosed.

Abstract: A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.

Abstract: A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal. A resistor has a first terminal connected to the gate terminal and has a second terminal connected to an auxiliary pad. When the electronic circuit is operating in a test phase and is configured for receiving a test signal for performing the test of the transistor, the auxiliary pad is electrically floating. When the electronic circuit is operating in a normal phase and is configured for receiving a supply voltage, the auxiliary pad is electrically connected to a voltage value smaller than the sum of the voltage value of the source terminal with the threshold voltage value of the transistor.

Abstract: The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal. A resistor has a first terminal connected to the gate terminal and has a second terminal connected to an auxiliary pad. When the electronic circuit is operating in a test phase and is configured for receiving a test signal for performing the test of the transistor, the auxiliary pad is electrically floating. When the electronic circuit is operating in a normal phase and is configured for receiving a supply voltage, the auxiliary pad is electrically connected to a voltage value smaller than the sum of the voltage value of the source terminal with the threshold voltage value of the transistor.