Patents by Inventor Mauro Giacomini
Mauro Giacomini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230168300Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.Type: ApplicationFiled: November 8, 2022Publication date: June 1, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Mauro GIACOMINI, Fabio Enrico Carlo DISEGNI, Rajesh NARWAL, Pravesh Kumar SAINI, Mayankkumar HARESHBHAI NIRANJANI
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Patent number: 10651641Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.Type: GrantFiled: June 29, 2017Date of Patent: May 12, 2020Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Mauro Giacomini, Rajesh Narwal, Pravesh Kumar Saini
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Patent number: 10591939Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.Type: GrantFiled: October 16, 2018Date of Patent: March 17, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Carmelo Burgio, Mauro Giacomini
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Publication number: 20190050014Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.Type: ApplicationFiled: October 16, 2018Publication date: February 14, 2019Inventors: Carmelo Burgio, Mauro Giacomini
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Patent number: 10126768Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.Type: GrantFiled: December 28, 2016Date of Patent: November 13, 2018Assignee: STMicroelectronics S.r.l.Inventors: Carmelo Burgio, Mauro Giacomini
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Publication number: 20180175606Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.Type: ApplicationFiled: June 29, 2017Publication date: June 21, 2018Inventors: Mauro Giacomini, Rajesh Narwal, Pravesh Kumar Saini
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Publication number: 20170329360Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.Type: ApplicationFiled: December 28, 2016Publication date: November 16, 2017Inventors: Carmelo Burgio, Mauro Giacomini
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Patent number: 9432041Abstract: A method of calibrating a thermometer-code SAR-A/D converter is provided. The thermometer-code SAR-A/D converter includes an Nbit-bit digital-to-analog converter (DAC) for outputting an Nbit-bit output code. The DAC includes a first subconverter having a plurality of NTh thermometer elements Tj and a second subconverter having a plurality of NBin binary-weighted elements. The Nbit output code is equal to the sum of NBitTh and NBitBin where NTh=2NBitTh and NBitBin is equal to NBin=NBitBin. The calibration method includes determining an Integral Non-Linearity error value (?R) of an Rth thermometer-code level of the thermometer elements. The method further includes reducing the highest of the error value ?R to obtain a reduced error value, and generating the output code according to said reduced error.Type: GrantFiled: April 10, 2015Date of Patent: August 30, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Mauro Giacomini, Carmelo Burgio
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Patent number: 9362937Abstract: The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale.Type: GrantFiled: August 25, 2015Date of Patent: June 7, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Carmelo Burgio, Mauro Giacomini
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Publication number: 20160149583Abstract: The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale.Type: ApplicationFiled: August 25, 2015Publication date: May 26, 2016Inventors: Carmelo BURGIO, Mauro GIACOMINI
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Publication number: 20150303933Abstract: A method of calibrating a thermometer-code SAR-A/D converter is provided. The thermometer-code SAR-A/D converter includes an Nbit-bit digital-to-analog converter (DAC) for outputting an Nbit-bit output code. The DAC includes a first subconverter having a plurality of NTh thermometer elements Tj and a second subconverter having a plurality of NBin binary-weighted elements. The Nbit output code is equal to the sum of NBitTh and NBitBin where NTh=2NBitTh and NBitBin is equal to NBin=NBitBin. The calibration method includes determining an Integral Non-Linearity error value (?R) of an Rth thermometer-code level of the thermometer elements. The method further includes reducing the highest of the error value ?R to obtain a reduced error value, and generating the output code according to said reduced error.Type: ApplicationFiled: April 10, 2015Publication date: October 22, 2015Inventors: Mauro GIACOMINI, Carmelo BURGIO
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Patent number: 8860517Abstract: An oscillator circuit including a first capacitor provided with a first terminal; a resistor provided with a reference terminal; a first current generator provided with a connection terminal; a second current generator provided with a second connection terminal. Further, the circuit includes a switching matrix between the first and second generators and resistor and the at least one first capacitor.Type: GrantFiled: June 15, 2012Date of Patent: October 14, 2014Assignee: STMicroelectronics S.R.L.Inventor: Mauro Giacomini
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Patent number: 8605398Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.Type: GrantFiled: August 6, 2009Date of Patent: December 10, 2013Assignees: Freescale Semiconductor, Inc., STMicroelectronics SRLInventors: Hubert Bode, Mauro Giacomini
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Publication number: 20120326796Abstract: An oscillator circuit including a first capacitor provided with a first terminal; a resistor provided with a reference terminal; a first current generator provided with a connection terminal; a second current generator provided with a second connection terminal. Further, the circuit includes a switching matrix between the first and second generators and resistor and the at least one first capacitor.Type: ApplicationFiled: June 15, 2012Publication date: December 27, 2012Applicant: STMicroelectronics S.r.l.Inventor: Mauro Giacomini
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Patent number: 8264389Abstract: An analog-to-digital converter has a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components. The converter includes a first generator configured to generate a first analog value, a digital-to-analog converter configured to generate a second analog value, a second generator configured to generate a digital value from the comparison of the first analog value with respect to the second analog value, a controller configured to receive a signal indicating a test mode and to generate a configuration signal to the first generator, to receive the digital value and generate a control signal to control the generation of the second analog value, and to generate from the digital value an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.Type: GrantFiled: August 18, 2010Date of Patent: September 11, 2012Assignee: STMicroelectronics S.r.L.Inventors: Gianluca Farabegoli, Mauro Giacomini, Marco Losi
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Publication number: 20120134060Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.Type: ApplicationFiled: August 6, 2009Publication date: May 31, 2012Applicants: Stmicroelectronics SRL, Freescale Semiconductor, Inc.Inventors: Hubert Bode, Mauro Giacomini
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Publication number: 20110043394Abstract: A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components.Type: ApplicationFiled: August 18, 2010Publication date: February 24, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Gianluca Farabegoli, Mauro Giacomini, Marco Losi
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Patent number: 6693829Abstract: A memory device implements a reading operation. The memory device includes first, second, and third memory cells; a read circuit coupled to the memory cells and operable to read first, second, and third values, respectively, from the first, second, and third memory cells; and a comparison circuit coupled to the read circuit and operable to compare the first and second values with fourth and fifth predetermined values and to generate a data-valid signal that indicates that the third value is valid if the first and second values equal the fourth and fifth values, respectively. The memory device may further include a selection circuit coupled to the read circuit and to the comparison circuit and operable to couple the third value to a data bus in response to the data-valid signal.Type: GrantFiled: February 5, 2002Date of Patent: February 17, 2004Assignee: STMicroelectronics S.R.l.Inventors: Irene Babudri, Mauro Giacomini
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Publication number: 20020141241Abstract: A memory device implements a reading operation that comprises:Type: ApplicationFiled: February 5, 2002Publication date: October 3, 2002Applicant: STMicroelectronics S.r.I.Inventors: Irene Babudri, Mauro Giacomini