Patents by Inventor Mauro Kobrinksy

Mauro Kobrinksy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vias in composite IC chip structures
    Patent number: 11694986
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast
  • VIAS IN COMPOSITE IC CHIP STRUCTURES
    Publication number: 20220037281
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Application
    Filed: October 13, 2021
    Publication date: February 3, 2022
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast
  • Vias in composite IC chip structures
    Patent number: 11205630
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast
  • VIAS IN COMPOSITE IC CHIP STRUCTURES
    Publication number: 20210098407
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast