Abstract: The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into account the temporal and spatial correlations in the picture.

Abstract: An integrated circuit for manipulating digitized video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, reordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device has memory for temporarily storing sequences to be manipulated and data read from the external memory; a circuit for decoding information about the manipulations to be performed; address circuitry for transferring the data between the device and the external memory; circuitry for configuring the device by means of a remote processing unit; circuitry for processing the data read from the external memory; and circuitry for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

Abstract: The video control circuit is particularly adapted to multimedia applicati, wherein image transmission services are offered in addition to usual telephone speech and data transmission services. The circuit is capable of processing both photographic and graphic video images, satisfying both the relevant CCIR standards and the specifications proper to personal computers, VGA EGA, etc. so as to allow the representation of either types of images on an only type of display. To this end, it generates both timings proper to the CCIR standards, for a resolution of 720 columns per 480 lines, with an upper representation limit of graphic planes of 1024 columns per 1024 lines.

Abstract: An electronic circuit for generating error detection codes in digital sigs organized into serial data blocks, which derives the error code from the coefficients of a remainder polynomial obtained from the division of a dividend polynomial, whose coefficients are the bits of each serial block, and a convenient divisor polynomial. The circuit has a shift register wherein at the beginning of each serial data block the reset and the first datum load are performed in a single clock interval.

Abstract: A multimedia protocol interface for 64K Kbit/s data flow, organized accorg to the frame structure specified in CCITT Recommendation H221 and transmitted and received according to the standard 64 kbit/s protocol or 256 kbit/s 10 M protocol, adapted to operate autonomously or aided by an external microprocessor and has a receiver, a transmitter, a control block and circuitry for the local test of the operation of the interface itself. The external microprocessor can read both the received data and the information relevant to the receiver conditions, and can also send data to be transmitted or can read information relevant to the transmitter conditions. The receiver receives the data and clock and synchronism signals and emits at the output the received data, associated with timing signals useful for the external devices connected to the interface for data recovery. Analogously, the transmitter emits the data, receives clock an synchronism signals and supplies data and timings to the external devices.