Abstract: A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a control word and provides a clock signal on the output terminal. The ring oscillator circuit includes a control architecture including a plurality of control blocks receiving respective bits of the control word and coupled to the delay stages of the ring. Each control block has at least a bistable element capable of receiving, storing and sending a bit of the control word to a multiplexer coupled to a respective delay stage in stable operating conditions of the ring.

Abstract: A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a control word and provides a clock signal on the output terminal. The ring oscillator circuit includes a control architecture including a plurality of control blocks receiving respective bits of the control word and coupled to the delay stages of the ring. Each control block has at least a bistable element capable of receiving, storing and sending a bit of the control word to a multiplexer coupled to a respective delay stage in stable operating conditions of the ring.

Abstract: A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a control word and provides a clock signal on the output terminal. The ring oscillator circuit includes a control architecture including a plurality of control blocks receiving respective bits of the control word and coupled to the delay stages of the ring. Each control block has at least a bistable element capable of receiving, storing and sending a bit of the control word to a multiplexer coupled to a respective delay stage in stable operating conditions of the ring.

Abstract: A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.

Abstract: A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.

Abstract: A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a control word and provides a clock signal on the output terminal. The ring oscillator circuit includes a control architecture including a plurality of control blocks receiving respective bits of the control word and coupled to the delay stages of the ring. Each control block has at least a bistable element capable of receiving, storing and sending a bit of the control word to a multiplexer coupled to a respective delay stage in stable operating conditions of the ring.

Abstract: A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.

Abstract: A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.