Abstract: A non-volatile memory cell 10 can be fabricated by doping a semiconductor substrate 8 to form source 12 and drain 14 such that at least one small undoped region remains in source 12. A first insulation layer 26a is formed over the source 12 such that the thickness of the layer is less over the undoped region than the doped region while insulation regions 26b and 20 are simultaneously formed over the drain 14 and channel 16 regions. The insulation layer 26a formed above the undoped region of the source 12 is etched to form a tunnel window 28 and then a thin insulation layer is formed over the tunnel window 28. A conductive floating gate 16 is formed over a portion of the first insulation layer 26a which includes the tunnel window 28, over the channel region 16 and over a portion of the second insulation region 26b. Next, an insulation region 24 is formed over the floating gate 16 and a control gate 18 is formed over the insulation region 24. Other structures and methods are also disclosed.