Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: Throughput and accuracy of testing of a semiconductor device is improved by forming the contacts to allow the leads of a packaged semiconductor device to pass through the contacts. Both AC and DC testing may be done because the contact length is substantially shortened.

Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: An integrated device test system (10, 40) having AC and DC measurement modes of operation comprises a drive circuit (11, 41), a programmable measurement unit (12) and a switch (18). The drive circuit (11, 41) may be a current mode drive circuit (11) or a voltage mode drive circuit (41). The drive circuit (11, 41) is coupled to the programmable measurement unit (12) and a device under test (64). In a DC mode of operation, the switch (18) is configured to couple a sense terminal (39) with one end of an isolation resistor (66). A second end of the isolation resistor (66) is connected to a pin (63) of the device under test (64). In an AC mode of operation, the switch (18) is configured to couple the sense terminal (39) with the drive circuit (11, 41) and the force terminal (35) of the programmable measurement unit (12).

Abstract: A cantilever spring (16) and a method for temporarily coupling a semiconductor package (36) to a transmission line (14) by means of the cantilever spring (16). The cantilever (16) has first and second pressure points (22, 32) that contact the transmission line (14). A force is applied to a third pressure point (32) which moves the first and second pressure points in opposite directions along the transmission line (14). In addition, the force on the third pressure point moves an end (21) of the cantilever spring (16) in a direction away from the transmission line (14). A lead (37) from the semiconductor package (36) contacts a portion of the end (21). Electrical signals are transmitted between the semiconductor package (36) and a tester via the cantilever spring (16) and the transmission line (14), wherein the electrical signals are for testing a semiconductor device (30).

Abstract: An integrated device test system (10, 40) having AC and DC measurement modes of operation comprises a drive circuit (11, 41), a programmable measurement unit (12) and a switch (18). The drive circuit (11, 41) may be a current mode drive circuit (11) or a voltage mode drive circuit (41). The drive circuit (11, 41) is coupled to the programmable measurement unit (12) and a device under test (64). In a DC mode of operation, the switch (18) is configured to couple a sense terminal (39) with one end of an isolation resistor (66). A second end of the isolation resistor (66) is connected to a pin (63) of the device under test (64). In an AC mode of operation, the switch (18) is configured to couple the sense terminal (39) with the drive circuit (11, 41) and the force terminal (35) of the programmable measurement unit (12).

Abstract: A test fixture operates under the control of a computer to make automatic correction in test contact spacing between the test fixture contact pins and the circuit under test. The computer detects continuity test failures and raises the test fixture to bring the test contact pins into proximity with the leads of the circuit under test. The computer controls rotation of a motor that drives a screw and moves a shaft and wedge assembly in the horizontal direction. A push rod is attached to the test fixture by way of a base plate and angle brackets. The push rod resting on the wedge slide up and down to raise and lower the test fixture.

Abstract: The present invention includes a method for transporting articles (24), and a pick and place apparatus (10) for implementing the method. The apparatus includes a suction tube (12) coupled to a pickup cam (11) and a pin (22) coupled to a hold-down cam (18). The pickup cam (11) and the hold-down cam (18) share a common cam shaft (15). In addition, the suction tube (12) is coupled to a pressure reduction apparatus (16) which is enabled throughout the transport process. The cam shaft (15) is rotated in a first direction to couple the article (24) to a suction cup (14). The article (24) is transported to a desired location and released by reversing the direction of rotation of the cam shaft (15). The article (24) is released by the pin (22) pushing the article (24) away from the suction cup (14).

Abstract: A handler (11) which transports a number of packaged semiconductor devices (12) in a boat (23) to a test head (14) and tests the devices (12) is provided. The handler (11) has an input staging section (29), a testing section (31) which is adjacent to the test head (14), and an output staging section (36). A boat transport (27a, 27b) moves the boat (23) from the input staging section (29) to the testing section (31) and from the testing section (31) to the output staging section (36). The boat transport (27a, 27b) operates during the device testing to provide substantially parallel operation of the testing and handling steps. A boat lift (39) moves the boat (23) to the test head (14) to allow the packaged semiconductor devices (12) to remain in the boat (23) during testing.

Abstract: An ECL logic circuit having differential inputs and differential outputs and programmable propagation delay time is provided. The differential inputs are coupled to a first differential amplifier as is done on a conventional differential ECL circuit. A second feedback differential amplifier is coupled to the collectors of the first differential amplifier. Current in the first differential amplifier is normally constant, whereas current in the feedback differential amplifier can be programmably adjusted. By adjusting the current in the feedback differential amplifier the feedback differential amplifier loads the logic circuit forcing a voltage swing which is up to double that normally provided by the first differential amplifier, therefore increasing the time required for either output to change from a logic LOW to a logic HIGH. This delay results in a variable propagation delay which is controlled by adjusting current flow in the feedback differential amplifier.

Abstract: An interface apparatus for coupling a multi-channel tester to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units are coupled to each test channel of the multi-channel tester. Some of the terminal electronics units are coupled to each other in parallel by at least one stimulus shift register, which serves to divide a serial stimulus vector among the terminal electronics units, and one response shift register, which serve to assembly the response data from several terminal electronics units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester. The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.

Abstract: An apparatus for use in high speed digital testing of high pin count logic circuits is provided wherein a plurality of terminal electronics units are connected in series to each other and to one channel of a multi-channel tester. Each pin electronics unit stores a test vector from the test channel in a first mode, and applies the test vector to the circuit under test at high speed in a second mode. Each pin electronics unit can also store response data from the circuit under test.

Abstract: A digital time base generator circuit is provided having a first phase locked loop for multiplying a reference frequency by an integer amount and a second phase locked loop for multiplying the reference frequency by a different integer amount. The first and second multiplied reference frequencies are then divided back down to the original reference frequency by two dual modulus frequency dividers. In this manner a start signal and a stop signal are generated such that the frequency of the start and stop reference signals is the same as the original reference frequency and the time delay between an edge of the start signal and edge of the stop signal can be changed by altering the mode of either of the dual modulus frequency dividers.

Abstract: A signal of a known period is transmitted through a semiconductor device to the set input of a flip-flop. The reset input of the flip-flop receives the original signal delayed by one-half the known period. The inverted and noninverted outputs of the flip-flop are then filtered and input to a leveling circuit and a differential amplifier. The leveling circuit adjusts the outputs of the flip-flop to produce signals of constant known amplitude. The output of the differential amplifier represents the delay of the signal through the semiconductor device.

Abstract: A mechanical clutch is described having a spring loaded clutch ring with a drive pin extending through a hole in a hub of a wheel and into a notch of a drive shaft. When pressure is exerted on the outer portion of the drive wheel, the spring is compressed and the drive pin is removed from the notch of the drive shaft. This allows the drive shaft to turn freely within the wheel and hub.

Abstract: An integrated circuit handler provides very high throughput rates and very low manual labor requirements. A sleeve handler portion provides nearly all of the sleeve handling needs of the handler, receiving periodic inputs of a plurality of sleeves, orienting and unloading the sleeves, reloading the sleeves and binning the sleeves according to output category. Once out of the sleeves, the integrated circuits are handled, in turn, by an input buffer, a transport mechanism which presents the integrated circuits to a workstation, a sort mechanism and an output buffer/sleeve loader mechanism. The particular embodiment disclosed in detail comprises a handler optimized for handling SOIC devices. No gravity-driven mechanisms are used in the handler. Throughput rates up to 60,000 parts per hour and more are possible.

Abstract: A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.

Abstract: An output buffer apparatus for an integrated circuit handler comprises a plurality of buffer tracks adapted to slidably contain integrated circuits. The tracks are designed to engage only the body portions of the integrated circuits so as to avoid lead damage. A belt running parallel to each track carries paddles which interrupt the path of the integrated circuits thereon. Movement of the belt moves the paddles so that the functions of stopping further movement down the track and forcing the integrated circuits off the output end of the track are performed. Thus, the buffer tracks also serve a sleeve loading function of the handler.

Abstract: A buffer and injector apparatus for use in an automated article handling system is adapted to operate between one process which periodically outputs a plurality of articles and another which requires a steady input of individual articles. A particular embodiment is adapted for use in an automated integrated circuit handler between a sleeve unloader and a transport apparatus. Integrated circuits are slideably contained by a buffer track and moved thereon by a belt. Neither the track nor the belt contact the leads of the integrated circuits. A sensor mid-way down the track triggers the sleeve unloader to input more integrated circuits. An injector apparatus at the output end of the track comprises a wheel which engages each integrated circuit until the transport apparatus is ready, then rotates rapidly to inject the integrated circuit into the transport and simultaneously engage another integrated circuit.

Abstract: A system and method for detecting when a satellite is within range of a small, battery-operated, portable transmitter so as to activate the transmitter only when the satellite is within range of the transmitter. The electronic system utilizes a sensitive radio-frequency receiver which can be tuned to receive a unique down-link signal from the orbiting satellite. The signal is amplified and demodulated and then input to a microprocessor. Information is stored in the memory of the microprocessor which identifies the unique down-link signal. The microprocessor compares the demodulated signal with the stored signal and if the two match, the earth-based transmitter is turned on and allowed to transmit for an interval of time. The microprocessor is maintained in a normally "full-stop" mode wherein power to the microprocessor is essentially turned off, and the microprocessor is periodically switched on so that it can check for the presence of the uniquely identifiable down-link signal which triggers transmission.