Abstract: Cover properties are extended in formal verification to reach an effective end-of-test stage for a design under test. A formal verification task for a design under test may be received at a verification system. A cover property asserted in the formal verification task may be identified. An additional condition may be implemented for the identified cover property to extend the identified cover property to cause performance of the formal verification task to generate a trace to reach an effective end-of-test stage for the design under test in the event of a failure of the cover property.

Abstract: Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

Abstract: A fuzzy scoreboard can compute, using a signature function, a first signature of an expected data stream associated with an input data stream that is being inputted to a design-under-test (DUT) for a datapath test. The first signature of the expected data stream can be stored without storing the expected data stream. The fuzzy scoreboard can also compute, using the same signature function, a second signature of an output data stream that is outputted from the DUT during the datapath test. The first signature can be compared with the second signature to determine whether there is a match. Storing the first signature of the expected data stream without storing the expected data stream can reduce the memory space consumed by the fuzzy scoreboard.

Abstract: An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.

Abstract: Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

Abstract: Bit-reduction in a verification processes for memory arrays is disclosed. Properties are determined for verification of a circuit that includes a memory array. Circuit data for the circuit is received in a verification environment. When it is determined that the circuit includes a memory array, an address for the memory array is sampled as part of a read operation during verification for the circuit. A determination may be made that the circuit is in compliance with a property of the properties based at least in part on compliance of the read operation with a predetermined model. The sampling of the address replicates a delay expected in physical read operation of the memory array, but with reduced bits communicated or generated per cycle in the verification process because output data is not sampled contrasting the physical read operation.