Abstract: Phase detectors are provided. In one example, The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Abstract: Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Abstract: Phase detectors are provided. In one example, The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Abstract: Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network (RCN) that resonates in response to both a first clock signal having a first phase and a second clock signal having a second phase. The RCN includes at least one rib coupled to at least one spine. The rib includes a first capacitive line configured to receive the first clock signal and provide, via a first capacitor, a first bias current to a first superconducting circuit. The rib further includes a second capacitive line configured to receive the second clock signal and provide, via a second capacitor, a second bias current to a second superconducting circuit. The rib further includes at least one inductive line configured to connect the first capacitive line with the second capacitive line forming a direct connection between the two capacitive lines.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network (RCN) that resonates in response to both a first clock signal having a first phase and a second clock signal having a second phase. The RCN includes at least one rib coupled to at least one spine. The rib includes a first capacitive line configured to receive the first clock signal and provide, via a first capacitor, a first bias current to a first superconducting circuit. The rib further includes a second capacitive line configured to receive the second clock signal and provide, via a second capacitor, a second bias current to a second superconducting circuit. The rib further includes at least one inductive line configured to connect the first capacitive line with the second capacitive line forming a direct connection between the two capacitive lines.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a sinusoidal clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and arranged as a standing wave resonator. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line is conductively coupled to an associated circuit and has a plurality of inductive couplings to the at least one resonator rib to inductively generate a clock current corresponding to the sinusoidal clock signal via each of the plurality of inductive couplings in an additive manner to provide functions for the associated circuit.

Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a sinusoidal clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and arranged as a standing wave resonator. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line is conductively coupled to an associated circuit and has a plurality of inductive couplings to the at least one resonator rib to inductively generate a clock current corresponding to the sinusoidal clock signal via each of the plurality of inductive couplings in an additive manner to provide functions for the associated circuit.

Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a sinusoidal clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and arranged as a standing wave resonator. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line is conductively coupled to an associated circuit and has a plurality of inductive couplings to the at least one resonator rib to inductively generate a clock current corresponding to the sinusoidal clock signal via each of the plurality of inductive couplings in an additive manner to provide functions for the associated circuit.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.