Patents by Inventor Max F. Hineman
Max F. Hineman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210407582Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Jaydip Bharatkumar Patel, Everardo Flores, III, Khaled Hasnat, Max F. Hineman
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Patent number: 11195575Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.Type: GrantFiled: June 25, 2020Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Jaydip Bharatkumar Patel, Everardo Flores, III, Khaled Hasnat, Max F. Hineman
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Patent number: 9837604Abstract: Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.Type: GrantFiled: January 5, 2017Date of Patent: December 5, 2017Assignee: INTEL CORPORATIONInventors: Lequn J. Liu, Ugo Russo, Max F. Hineman
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Publication number: 20170125671Abstract: Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 5, 2017Publication date: May 4, 2017Inventors: Lequn J. Liu, Ugo Russo, Max F. Hineman
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Patent number: 9608042Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.Type: GrantFiled: February 5, 2016Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Fabio Pellizzer, Giulio Albini, Stephen W. Russell, Max F. Hineman, Sanjay Rangan
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Patent number: 9559146Abstract: Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.Type: GrantFiled: December 23, 2014Date of Patent: January 31, 2017Assignee: INTEL CORPORATIONInventors: Lequn J. Liu, Ugo Russo, Max F. Hineman
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Publication number: 20160307963Abstract: In one embodiment, a method associated with forming a memory cell that comprises programmable material comprises forming a stack comprising sacrificial material over lower conductive material. The sacrificial material is first patterned in a first direction to form a sacrificial line. After the first patterning, second patterning is conducted of the sacrificial material of the sacrificial line in a second direction that crosses the first direction to form a sacrificial elevationally-extending projection from the sacrificial line. The sacrificial projection is replaced with phase change material to form an elevationally-extending projection comprising the phase change material. The phase change material projection is incorporated into one of the programmable material or a selector device component of the memory cell being formed. Other embodiments are disclosed.Type: ApplicationFiled: April 20, 2015Publication date: October 20, 2016Inventors: Max F. Hineman, Jong Won Lee
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Publication number: 20160233271Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 5, 2016Publication date: August 11, 2016Inventors: Fabio Pellizzer, Giulio Albini, Stephen W. Russell, Max F. Hineman, Sanjay Rangan
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Publication number: 20160181324Abstract: Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Lequn J. Liu, Ugo Russo, Max F. Hineman
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Patent number: 9299747Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.Type: GrantFiled: November 24, 2014Date of Patent: March 29, 2016Assignee: INTEL CORPORATIONInventors: Fabio Pellizzer, Giulio Albini, Stephen W. Russell, Max F. Hineman, Sanjay Rangan
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Patent number: 9231202Abstract: A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.Type: GrantFiled: June 19, 2013Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Kiran Pangal, Max F. Hineman
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Patent number: 9082714Abstract: Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.Type: GrantFiled: September 22, 2011Date of Patent: July 14, 2015Assignee: Intel CorporationInventors: Randy J. Koval, Max F. Hineman, Ronald A. Weimer, Vinayak K. Shamanna, Thomas M. Graettinger, William R. Kueber, Christopher Larsen, Alex J. Schrinsky
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Publication number: 20140374686Abstract: A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: Kiran Pangal, Max F. Hineman
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Patent number: 8673787Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: GrantFiled: June 21, 2011Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock
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Publication number: 20130264628Abstract: Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 22, 2011Publication date: October 10, 2013Inventors: Randy J. Koval, Max F. Hineman, Ronald A. Weimer, Vinayak K. Shamanna, Thomas M. Graettinger, William R. Kueber, Christopher Larsen, Alex J. Schrinsky
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Publication number: 20110250759Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: ApplicationFiled: June 21, 2011Publication date: October 13, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock
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Patent number: 7985692Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: GrantFiled: January 23, 2008Date of Patent: July 26, 2011Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock
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Patent number: 7615164Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.Type: GrantFiled: June 23, 2004Date of Patent: November 10, 2009Assignee: Micron Technology, Inc.Inventors: Bradley J. Howard, Max F. Hineman
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Publication number: 20080128389Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: ApplicationFiled: January 23, 2008Publication date: June 5, 2008Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock
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Patent number: 7344975Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: GrantFiled: August 26, 2005Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock