Patents by Inventor Maxi Chang
Maxi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11094545Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: GrantFiled: July 16, 2019Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Publication number: 20190341263Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 10388531Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: GrantFiled: September 27, 2017Date of Patent: August 20, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Publication number: 20180019133Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: ApplicationFiled: September 27, 2017Publication date: January 18, 2018Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 9779947Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: January 6, 2016Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin
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Publication number: 20160196979Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: January 6, 2016Publication date: July 7, 2016Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 9252224Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: August 28, 2014Date of Patent: February 2, 2016Assignee: Taiwan semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Harry-Hak-Lay Chuang
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Publication number: 20140367802Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: August 28, 2014Publication date: December 18, 2014Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, JUNG-HUI KAO, Yuan-Tien Tu, HUAN-JUST LIN, Chih-Tang Peng, Pei-Ren Jeng, BAO-RU YOUNG, HARRY-HAK-LA Y CHUANG
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Patent number: 8822283Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: September 24, 2011Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
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Publication number: 20130056837Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: September 24, 2011Publication date: March 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
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Patent number: 8373199Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: GrantFiled: July 29, 2011Date of Patent: February 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Wen-Chin Yang, Chien-Liang Chen, Chung-Hua Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Publication number: 20110278646Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: ApplicationFiled: July 29, 2011Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Wen-Chin Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Patent number: 8003467Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: GrantFiled: April 30, 2009Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Wen-Chih Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Publication number: 20100109088Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: ApplicationFiled: April 30, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Wen-Chih Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang